Commit 793ee362 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'ocelot-phylink' 



Vladimir Oltean says:

====================
Convert ocelot to phylink

The ocelot switchdev and felix dsa drivers are interesting because they
target the same class of hardware switches but used in different modes.

Colin has an interesting use case where he wants to use a hardware
switch supported by the ocelot switchdev driver with the felix dsa
driver.

So far, the existing hardware revisions were similar between the ocelot
and felix drivers, but not completely identical. With identical hardware,
it is absurd that the felix driver uses phylink while the ocelot driver
uses phylib - this should not be one of the differences between the
switchdev and dsa driver, and we could eliminate it.

Colin will need the common phylink support in ocelot and felix when
adding a phylink_pcs driver for the PCS1G block inside VSC7514, which
will make the felix driver work with either the NXP or the Microchip PCS.

As usual, Alex, Horatiu, sorry for bugging you, but it would be
appreciated if you could give this a quick run on actual VSC7514
hardware (which I don't have) to make sure I'm not introducing any
breakage.
====================

Fixes: 0f06a678 ("samples: Add an IPv6 "-6" option to the pktgen scripts")
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents e871ee69 e6e12df6

drivers/net/dsa/ocelot/felix.c

+5 −104
Original line number Diff line number Diff line
@@ -796,23 +796,6 @@ static int felix_vlan_del(struct dsa_switch *ds, int port, 
	return ocelot_vlan_del(ocelot, port, vlan->vid);

}



static int felix_port_enable(struct dsa_switch *ds, int port,

			     struct phy_device *phy)

{

	struct ocelot *ocelot = ds->priv;



	ocelot_port_enable(ocelot, port, phy);



	return 0;

}



static void felix_port_disable(struct dsa_switch *ds, int port)

{

	struct ocelot *ocelot = ds->priv;



	return ocelot_port_disable(ocelot, port);

}



static void felix_phylink_validate(struct dsa_switch *ds, int port,

				   unsigned long *supported,

				   struct phylink_link_state *state)
@@ -841,25 +824,9 @@ static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, 
					phy_interface_t interface)

{

	struct ocelot *ocelot = ds->priv;

	struct ocelot_port *ocelot_port = ocelot->ports[port];

	int err;



	ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,

			 DEV_MAC_ENA_CFG);



	ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);



	err = ocelot_port_flush(ocelot, port);

	if (err)

		dev_err(ocelot->dev, "failed to flush port %d: %d\n",

			port, err);



	/* Put the port in reset. */

	ocelot_port_writel(ocelot_port,

			   DEV_CLOCK_CFG_MAC_TX_RST |

			   DEV_CLOCK_CFG_MAC_RX_RST |

			   DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),

			   DEV_CLOCK_CFG);

	ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface,

				     FELIX_MAC_QUIRKS);

}



static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port,
@@ -870,75 +837,11 @@ static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, 
				      bool tx_pause, bool rx_pause)

{

	struct ocelot *ocelot = ds->priv;

	struct ocelot_port *ocelot_port = ocelot->ports[port];

	struct felix *felix = ocelot_to_felix(ocelot);

	u32 mac_fc_cfg;



	/* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and

	 * PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is

	 * integrated is that the MAC speed is fixed and it's the PCS who is

	 * performing the rate adaptation, so we have to write "1000Mbps" into

	 * the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default

	 * value).

	 */

	ocelot_port_writel(ocelot_port,

			   DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),

			   DEV_CLOCK_CFG);



	switch (speed) {

	case SPEED_10:

		mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3);

		break;

	case SPEED_100:

		mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2);

		break;

	case SPEED_1000:

	case SPEED_2500:

		mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1);

		break;

	default:

		dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",

			port, speed);

		return;

	}



	/* handle Rx pause in all cases, with 2500base-X this is used for rate

	 * adaptation.

	 */

	mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;



	if (tx_pause)

		mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |

			      SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |

			      SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |

			      SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;



	/* Flow control. Link speed is only used here to evaluate the time

	 * specification in incoming pause frames.

	 */

	ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);



	ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);



	ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause);



	/* Undo the effects of felix_phylink_mac_link_down:

	 * enable MAC module

	 */

	ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |

			   DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);



	/* Enable receiving frames on the port, and activate auto-learning of

	 * MAC addresses.

	 */

	ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |

			 ANA_PORT_PORT_CFG_RECV_ENA |

			 ANA_PORT_PORT_CFG_PORTID_VAL(port),

			 ANA_PORT_PORT_CFG, port);



	/* Core: Enable port for frame transfer */

	ocelot_fields_write(ocelot, port,

			    QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);

	ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode,

				   interface, speed, duplex, tx_pause, rx_pause,

				   FELIX_MAC_QUIRKS);



	if (felix->info->port_sched_speed_set)

		felix->info->port_sched_speed_set(ocelot, port, speed);
@@ -1615,8 +1518,6 @@ const struct dsa_switch_ops felix_switch_ops = { 
	.phylink_mac_config		= felix_phylink_mac_config,

	.phylink_mac_link_down		= felix_phylink_mac_link_down,

	.phylink_mac_link_up		= felix_phylink_mac_link_up,

	.port_enable			= felix_port_enable,

	.port_disable			= felix_port_disable,

	.port_fdb_dump			= felix_fdb_dump,

	.port_fdb_add			= felix_fdb_add,

	.port_fdb_del			= felix_fdb_del,

drivers/net/dsa/ocelot/felix.h

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#define _MSCC_FELIX_H



#define ocelot_to_felix(o)		container_of((o), struct felix, ocelot)

#define FELIX_MAC_QUIRKS		OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION



/* Platform-specific information */

struct felix_info {

drivers/net/ethernet/mscc/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ config MSCC_OCELOT_SWITCH_LIB 
	select NET_DEVLINK

	select REGMAP_MMIO

	select PACKING

	select PHYLIB

	select PHYLINK

	tristate

	help

	  This is a hardware support library for Ocelot network switches. It is

drivers/net/ethernet/mscc/ocelot.c

+103 −70
Original line number Diff line number Diff line
@@ -377,7 +377,7 @@ static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 
	return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);

}



int ocelot_port_flush(struct ocelot *ocelot, int port)

static int ocelot_port_flush(struct ocelot *ocelot, int port)

{

	unsigned int pause_ena;

	int err, val;
@@ -429,63 +429,118 @@ int ocelot_port_flush(struct ocelot *ocelot, int port) 


	return err;

}

EXPORT_SYMBOL(ocelot_port_flush);



void ocelot_adjust_link(struct ocelot *ocelot, int port,

			struct phy_device *phydev)

void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,

				  unsigned int link_an_mode,

				  phy_interface_t interface,

				  unsigned long quirks)

{

	struct ocelot_port *ocelot_port = ocelot->ports[port];

	int speed, mode = 0;

	int err;



	ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,

			 DEV_MAC_ENA_CFG);



	ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);



	err = ocelot_port_flush(ocelot, port);

	if (err)

		dev_err(ocelot->dev, "failed to flush port %d: %d\n",

			port, err);



	/* Put the port in reset. */

	if (interface != PHY_INTERFACE_MODE_QSGMII ||

	    !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))

		ocelot_port_rmwl(ocelot_port,

				 DEV_CLOCK_CFG_MAC_TX_RST |

				 DEV_CLOCK_CFG_MAC_TX_RST,

				 DEV_CLOCK_CFG_MAC_TX_RST |

				 DEV_CLOCK_CFG_MAC_TX_RST,

				 DEV_CLOCK_CFG);

}

EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);



	switch (phydev->speed) {

void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,

				struct phy_device *phydev,

				unsigned int link_an_mode,

				phy_interface_t interface,

				int speed, int duplex,

				bool tx_pause, bool rx_pause,

				unsigned long quirks)

{

	struct ocelot_port *ocelot_port = ocelot->ports[port];

	int mac_speed, mode = 0;

	u32 mac_fc_cfg;



	/* The MAC might be integrated in systems where the MAC speed is fixed

	 * and it's the PCS who is performing the rate adaptation, so we have

	 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG

	 * (which is also its default value).

	 */

	if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||

	    speed == SPEED_1000) {

		mac_speed = OCELOT_SPEED_1000;

		mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;

	} else if (speed == SPEED_2500) {

		mac_speed = OCELOT_SPEED_2500;

		mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;

	} else if (speed == SPEED_100) {

		mac_speed = OCELOT_SPEED_100;

	} else {

		mac_speed = OCELOT_SPEED_10;

	}



	if (duplex == DUPLEX_FULL)

		mode |= DEV_MAC_MODE_CFG_FDX_ENA;



	ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);



	/* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and

	 * PORT_RST bits in DEV_CLOCK_CFG.

	 */

	ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),

			   DEV_CLOCK_CFG);



	switch (speed) {

	case SPEED_10:

		speed = OCELOT_SPEED_10;

		mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);

		break;

	case SPEED_100:

		speed = OCELOT_SPEED_100;

		mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);

		break;

	case SPEED_1000:

		speed = OCELOT_SPEED_1000;

		mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;

		break;

	case SPEED_2500:

		speed = OCELOT_SPEED_2500;

		mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;

		mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);

		break;

	default:

		dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",

			port, phydev->speed);

		dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",

			port, speed);

		return;

	}



	phy_print_status(phydev);



	if (!phydev->link)

		return;



	/* Only full duplex supported for now */

	ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |

			   mode, DEV_MAC_MODE_CFG);



	/* Disable HDX fast control */

	ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,

			   DEV_PORT_MISC);

	/* Handle RX pause in all cases, with 2500base-X this is used for rate

	 * adaptation.

	 */

	mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;



	/* SGMII only for now */

	ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,

			   PCS1G_MODE_CFG);

	ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);

	if (tx_pause)

		mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |

			      SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |

			      SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |

			      SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;



	/* Enable PCS */

	ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);

	/* Flow control. Link speed is only used here to evaluate the time

	 * specification in incoming pause frames.

	 */

	ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);



	/* No aneg on SGMII */

	ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);

	ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);



	/* No loopback */

	ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);

	ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause);



	/* Enable MAC module */

	/* Undo the effects of ocelot_phylink_mac_link_down:

	 * enable MAC module

	 */

	ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |

			   DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
@@ -502,39 +557,8 @@ void ocelot_adjust_link(struct ocelot *ocelot, int port, 
	/* Core: Enable port for frame transfer */

	ocelot_fields_write(ocelot, port,

			    QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);



	/* Flow control */

	ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |

			 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |

			 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |

			 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |

			 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),

			 SYS_MAC_FC_CFG, port);

	ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);

}

EXPORT_SYMBOL(ocelot_adjust_link);



void ocelot_port_enable(struct ocelot *ocelot, int port,

			struct phy_device *phy)

{

	/* Enable receiving frames on the port, and activate auto-learning of

	 * MAC addresses.

	 */

	ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |

			 ANA_PORT_PORT_CFG_RECV_ENA |

			 ANA_PORT_PORT_CFG_PORTID_VAL(port),

			 ANA_PORT_PORT_CFG, port);

}

EXPORT_SYMBOL(ocelot_port_enable);



void ocelot_port_disable(struct ocelot *ocelot, int port)

{

	struct ocelot_port *ocelot_port = ocelot->ports[port];



	ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);

	ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);

}

EXPORT_SYMBOL(ocelot_port_disable);

EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);



static void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,

					 struct sk_buff *clone)
@@ -1956,6 +1980,15 @@ void ocelot_init_port(struct ocelot *ocelot, int port) 
	/* Disable source address learning for standalone mode */

	ocelot_port_set_learning(ocelot, port, false);



	/* Set the port's initial logical port ID value, enable receiving

	 * frames on it, and configure the MAC address learning type to

	 * automatic.

	 */

	ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |

			 ANA_PORT_PORT_CFG_RECV_ENA |

			 ANA_PORT_PORT_CFG_PORTID_VAL(port),

			 ANA_PORT_PORT_CFG, port);



	/* Enable vcap lookups */

	ocelot_vcap_enable(ocelot, port);

}

drivers/net/ethernet/mscc/ocelot.h

+4 −7
Original line number Diff line number Diff line
@@ -12,8 +12,7 @@ 
#include <linux/etherdevice.h>

#include <linux/if_vlan.h>

#include <linux/net_tstamp.h>

#include <linux/phy.h>

#include <linux/phy/phy.h>

#include <linux/phylink.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>
@@ -42,11 +41,9 @@ struct ocelot_port_tc { 
struct ocelot_port_private {

	struct ocelot_port port;

	struct net_device *dev;

	struct phy_device *phy;

	struct phylink *phylink;

	struct phylink_config phylink_config;

	u8 chip_port;



	struct phy *serdes;



	struct ocelot_port_tc tc;

};
@@ -107,7 +104,7 @@ u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 
void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);



int ocelot_probe_port(struct ocelot *ocelot, int port, struct regmap *target,

		      struct phy_device *phy);

		      struct device_node *portnp);

void ocelot_release_port(struct ocelot_port *ocelot_port);

int ocelot_devlink_init(struct ocelot *ocelot);

void ocelot_devlink_teardown(struct ocelot *ocelot);