Commit 793445cf authored by Shayne Chen's avatar Shayne Chen Committed by Felix Fietkau
Browse files

wifi: mt76: mt7996: update register for CFEND_RATE 



In newer chipsets, CFEND_RATE setting has been moved to different hw
module.

Fixes: 98686cd2 ("wifi: mt76: mt7996: add driver for MediaTek Wi-Fi 7 (802.11be) devices")
Signed-off-by: default avatarShayne Chen <shayne.chen@mediatek.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent eb1fdb9f

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

+1 −1
Original line number Diff line number Diff line
@@ -1690,7 +1690,7 @@ void mt7996_mac_set_timing(struct mt7996_phy *phy) 
	else

		val = MT7996_CFEND_RATE_11B;



	mt76_rmw_field(dev, MT_AGG_ACR0(band_idx), MT_AGG_ACR_CFEND_RATE, val);

	mt76_rmw_field(dev, MT_RATE_HRCR0(band_idx), MT_RATE_HRCR0_CFEND_RATE, val);

	mt76_clear(dev, MT_ARB_SCR(band_idx),

		   MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);

}

drivers/net/wireless/mediatek/mt76/mt7996/mmio.c

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ static const struct __base mt7996_reg_base[] = { 
	[WF_ETBF_BASE]		= { { 0x820ea000, 0x820fa000, 0x830ea000 } },

	[WF_LPON_BASE]		= { { 0x820eb000, 0x820fb000, 0x830eb000 } },

	[WF_MIB_BASE]		= { { 0x820ed000, 0x820fd000, 0x830ed000 } },

	[WF_RATE_BASE]		= { { 0x820ee000, 0x820fe000, 0x830ee000 } },

};



static const struct __map mt7996_reg_map[] = {

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

+8 −7
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ enum base_rev { 
	WF_ETBF_BASE,

	WF_LPON_BASE,

	WF_MIB_BASE,

	WF_RATE_BASE,

	__MT_REG_BASE_MAX,

};
@@ -235,13 +236,6 @@ enum base_rev { 
						 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \

						 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))



/* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */

#define MT_WF_AGG_BASE(_band)			__BASE(WF_AGG_BASE, (_band))

#define MT_WF_AGG(_band, ofs)			(MT_WF_AGG_BASE(_band) + (ofs))



#define MT_AGG_ACR0(_band)			MT_WF_AGG(_band, 0x054)

#define MT_AGG_ACR_CFEND_RATE			GENMASK(13, 0)



/* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */

#define MT_WF_ARB_BASE(_band)			__BASE(WF_ARB_BASE, (_band))

#define MT_WF_ARB(_band, ofs)			(MT_WF_ARB_BASE(_band) + (ofs))
@@ -300,6 +294,13 @@ enum base_rev { 
#define MT_WF_RMAC_RSVD0(_band)			MT_WF_RMAC(_band, 0x03e0)

#define MT_WF_RMAC_RSVD0_EIFS_CLR		BIT(21)



/* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */

#define MT_WF_RATE_BASE(_band)			__BASE(WF_RATE_BASE, (_band))

#define MT_WF_RATE(_band, ofs)			(MT_WF_RATE_BASE(_band) + (ofs))



#define MT_RATE_HRCR0(_band)			MT_WF_RATE(_band, 0x050)

#define MT_RATE_HRCR0_CFEND_RATE		GENMASK(14, 0)



/* WFDMA0 */

#define MT_WFDMA0_BASE				0xd4000

#define MT_WFDMA0(ofs)				(MT_WFDMA0_BASE + (ofs))