Commit 79250172 authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a779a0: Add SDHI support 



We use the shiny new CPG library for that.

Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201227174202.40834-5-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 8bb67d87

drivers/clk/renesas/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -148,6 +148,7 @@ config CLK_R8A77995 


config CLK_R8A779A0

	bool "R-Car V3U clock support" if COMPILE_TEST

	select CLK_RCAR_CPG_LIB

	select CLK_RENESAS_CPG_MSSR



config CLK_R9A06G032

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+15 −2
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>



#include "rcar-cpg-lib.h"

#include "renesas-cpg-mssr.h"



enum rcar_r8a779a0_clk_types {
@@ -32,6 +33,7 @@ enum rcar_r8a779a0_clk_types { 
	CLK_TYPE_R8A779A0_PLL1,

	CLK_TYPE_R8A779A0_PLL2X_3X,	/* PLL[23][01] */

	CLK_TYPE_R8A779A0_PLL5,

	CLK_TYPE_R8A779A0_SD,

	CLK_TYPE_R8A779A0_MDSEL,	/* Select parent/divider using mode pin */

	CLK_TYPE_R8A779A0_OSC,	/* OSC EXTAL predivider and fixed divider */

};
@@ -82,6 +84,9 @@ enum clk_ids { 
	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \

		 .offset = _offset)



#define DEF_SD(_name, _id, _parent, _offset)   \

	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)



#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \

	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL,	\

		 (_parent0) << 16 | (_parent1),		\
@@ -113,6 +118,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED(".pll5_div4",		CLK_PLL5_DIV4,	CLK_PLL5_DIV2,	2, 1),

	DEF_FIXED(".s1",		CLK_S1,		CLK_PLL1_DIV2,	2, 1),

	DEF_FIXED(".s3",		CLK_S3,		CLK_PLL1_DIV2,	4, 1),

	DEF_FIXED(".sdsrc",		CLK_SDSRC,	CLK_PLL5_DIV4,	1, 1),

	DEF_RATE(".oco",		CLK_OCO,	32768),



	/* Core Clock Outputs */
@@ -139,6 +145,8 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED("cbfusa",	R8A779A0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cp",		R8A779A0_CLK_CP,	CLK_EXTAL,	2, 1),



	DEF_SD("sd0",		R8A779A0_CLK_SD0,	CLK_SDSRC,	0x870),



	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),

	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),

	DEF_DIV6P1("csi0",	R8A779A0_CLK_CSI0,	CLK_PLL5_DIV4,	0x880),
@@ -168,6 +176,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("scif1",	703,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif3",	704,	R8A779A0_CLK_S1D8),

	DEF_MOD("scif4",	705,	R8A779A0_CLK_S1D8),

	DEF_MOD("sdhi0",	706,	R8A779A0_CLK_SD0),

	DEF_MOD("vin00",	730,	R8A779A0_CLK_S1D1),

	DEF_MOD("vin01",	731,	R8A779A0_CLK_S1D1),

	DEF_MOD("vin02",	800,	R8A779A0_CLK_S1D1),
@@ -213,8 +222,6 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("vspx3",	1031,	R8A779A0_CLK_S1D1),

};



static spinlock_t cpg_lock;



static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;

static unsigned int cpg_clk_extalr __initdata;

static u32 cpg_mode __initdata;
@@ -253,6 +260,12 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 
		div = cpg_pll_config->pll5_div;

		break;



	case CLK_TYPE_R8A779A0_SD:

		return cpg_sd_clk_register(core->name, base, core->offset,

					   __clk_get_name(parent), notifiers,

					   false);

		break;



	case CLK_TYPE_R8A779A0_MDSEL:

		/*

		 * Clock selectable between two parents and two fixed dividers