Commit 7908072d authored by Fuad Tabba's avatar Fuad Tabba Committed by Will Deacon
Browse files

arm64: Do not enable uaccess for invalidate_icache_range 



invalidate_icache_range() works on kernel addresses, and doesn't
need uaccess. Remove the code that toggles uaccess_ttbr0_enable,
as well as the code that emits an entry into the exception table
(via the macro invalidate_icache_by_line).

Changes return type of invalidate_icache_range() from int (which
used to indicate a fault) to void, since it doesn't need uaccess
and won't fault. Note that return value was never checked by any
of the callers.

No functional change intended.
Possible performance impact due to the reduced number of
instructions.

Reported-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reported-by: default avatarWill Deacon <will@kernel.org>
Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/


Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarArd Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-6-tabba@google.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 116b7f55

arch/arm64/include/asm/cacheflush.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -57,7 +57,7 @@ 
 *		- size   - region size

 *		- size   - region size

 */

 */

extern void __flush_icache_range(unsigned long start, unsigned long end);

extern void __flush_icache_range(unsigned long start, unsigned long end);

extern int  invalidate_icache_range(unsigned long start, unsigned long end);

extern void invalidate_icache_range(unsigned long start, unsigned long end);

extern void __flush_dcache_area(void *addr, size_t len);

extern void __flush_dcache_area(void *addr, size_t len);

extern void __inval_dcache_area(void *addr, size_t len);

extern void __inval_dcache_area(void *addr, size_t len);

extern void __clean_dcache_area_poc(void *addr, size_t len);

extern void __clean_dcache_area_poc(void *addr, size_t len);

arch/arm64/mm/cache.S

+1 −10
Original line number Original line Diff line number Diff line
@@ -90,21 +90,12 @@ SYM_FUNC_END(__flush_cache_user_range) 
 */

 */

SYM_FUNC_START(invalidate_icache_range)

SYM_FUNC_START(invalidate_icache_range)

alternative_if ARM64_HAS_CACHE_DIC

alternative_if ARM64_HAS_CACHE_DIC

	mov	x0, xzr

	isb

	isb

	ret

	ret

alternative_else_nop_endif

alternative_else_nop_endif





	uaccess_ttbr0_enable x2, x3, x4

	invalidate_icache_by_line x0, x1, x2, x3



	invalidate_icache_by_line x0, x1, x2, x3, 2f

	mov	x0, xzr

1:

	uaccess_ttbr0_disable x1, x2

	ret

	ret

2:

	mov	x0, #-EFAULT

	b	1b

SYM_FUNC_END(invalidate_icache_range)

SYM_FUNC_END(invalidate_icache_range)





/*

/*