Commit 78f94c08 authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
Browse files

RISC-V: KVM: Add ONE_REG interface for AIA CSRs 



We implement ONE_REG interface for AIA CSRs as a separate subtype
under the CSR ONE_REG interface.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarAtish Patra <atishp@rivosinc.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 7d50dd50

arch/riscv/include/uapi/asm/kvm.h

+8 −0
Original line number Diff line number Diff line
@@ -79,6 +79,10 @@ struct kvm_riscv_csr { 
	unsigned long scounteren;

};



/* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */

struct kvm_riscv_aia_csr {

};



/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */

struct kvm_riscv_timer {

	__u64 frequency;
@@ -107,6 +111,7 @@ enum KVM_RISCV_ISA_EXT_ID { 
	KVM_RISCV_ISA_EXT_ZIHINTPAUSE,

	KVM_RISCV_ISA_EXT_ZICBOM,

	KVM_RISCV_ISA_EXT_ZBB,

	KVM_RISCV_ISA_EXT_SSAIA,

	KVM_RISCV_ISA_EXT_MAX,

};
@@ -153,8 +158,11 @@ enum KVM_RISCV_SBI_EXT_ID { 
/* Control and status registers are mapped as type 3 */

#define KVM_REG_RISCV_CSR		(0x03 << KVM_REG_RISCV_TYPE_SHIFT)

#define KVM_REG_RISCV_CSR_GENERAL	(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)

#define KVM_REG_RISCV_CSR_AIA		(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)

#define KVM_REG_RISCV_CSR_REG(name)	\

		(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))

#define KVM_REG_RISCV_CSR_AIA_REG(name)	\

	(offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))



/* Timer registers are mapped as type 4 */

#define KVM_REG_RISCV_TIMER		(0x04 << KVM_REG_RISCV_TYPE_SHIFT)

arch/riscv/kvm/vcpu.c

+8 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ static const unsigned long kvm_isa_ext_arr[] = { 
	[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,

	[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,



	KVM_ISA_EXT_ARR(SSAIA),

	KVM_ISA_EXT_ARR(SSTC),

	KVM_ISA_EXT_ARR(SVINVAL),

	KVM_ISA_EXT_ARR(SVPBMT),
@@ -97,6 +98,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) 
	case KVM_RISCV_ISA_EXT_C:

	case KVM_RISCV_ISA_EXT_I:

	case KVM_RISCV_ISA_EXT_M:

	case KVM_RISCV_ISA_EXT_SSAIA:

	case KVM_RISCV_ISA_EXT_SSTC:

	case KVM_RISCV_ISA_EXT_SVINVAL:

	case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
@@ -520,6 +522,9 @@ static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, 
	case KVM_REG_RISCV_CSR_GENERAL:

		rc = kvm_riscv_vcpu_general_get_csr(vcpu, reg_num, &reg_val);

		break;

	case KVM_REG_RISCV_CSR_AIA:

		rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, &reg_val);

		break;

	default:

		rc = -EINVAL;

		break;
@@ -556,6 +561,9 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, 
	case KVM_REG_RISCV_CSR_GENERAL:

		rc = kvm_riscv_vcpu_general_set_csr(vcpu, reg_num, reg_val);

		break;

	case KVM_REG_RISCV_CSR_AIA:

		rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val);

		break;

	default:

		rc = -EINVAL;

		break;