Commit 78e98001 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.3-2023-02-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-next 



amd-drm-next-6.3-2023-02-03:

amdgpu:
- PCI hotplug fixes
- Allow S0ix without BIOS support
- GC11 fixes
- DCN 3.2.x fixes
- Enable freesync over PCon
- DSC fix
- DCN 3.1.4 fixes
- NBIO 4.3 fix
- Misc code cleanups and spelling fixes
- Temporarily disable S/G on DCN 2.1 and 3.1.2/3
- Fix and re-enable S/G on DCN 3.1.4
- Re-enable the AGP aperture on GMC 11.x

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230203220316.8580-1-alexander.deucher@amd.com
parents 1c0db6d8 69ed0c5d

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

+2 −6
Original line number Diff line number Diff line
@@ -1079,20 +1079,16 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) 
	 * S0ix even though the system is suspending to idle, so return false

	 * in that case.

	 */

	if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {

	if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))

		dev_warn_once(adev->dev,

			      "Power consumption will be higher as BIOS has not been configured for suspend-to-idle.\n"

			      "To use suspend-to-idle change the sleep mode in BIOS setup.\n");

		return false;

	}



#if !IS_ENABLED(CONFIG_AMD_PMC)

	dev_warn_once(adev->dev,

		      "Power consumption will be higher as the kernel has not been compiled with CONFIG_AMD_PMC.\n");

	return false;

#else

	return true;

#endif /* CONFIG_AMD_PMC */

	return true;

}



#endif /* CONFIG_SUSPEND */

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −1
Original line number Diff line number Diff line
@@ -4031,6 +4031,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) 


	amdgpu_gart_dummy_page_fini(adev);



	if (drm_dev_is_unplugged(adev_to_drm(adev)))

		amdgpu_device_unmap_mmio(adev);



}

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -2227,6 +2227,8 @@ amdgpu_pci_remove(struct pci_dev *pdev) 
	struct drm_device *dev = pci_get_drvdata(pdev);

	struct amdgpu_device *adev = drm_to_adev(dev);



	drm_dev_unplug(dev);



	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {

		pm_runtime_get_sync(dev->dev);

		pm_runtime_forbid(dev->dev);
@@ -2266,8 +2268,6 @@ amdgpu_pci_remove(struct pci_dev *pdev) 


	amdgpu_driver_unload_kms(dev);



	drm_dev_unplug(dev);



	/*

	 * Flush any in flight DMA operations from device.

	 * Clear the Bus Master Enable bit and then wait on the PCIe Device

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+13 −3
Original line number Diff line number Diff line
@@ -606,12 +606,21 @@ psp_cmd_submit_buf(struct psp_context *psp, 
	int timeout = 20000;

	bool ras_intr = false;

	bool skip_unsupport = false;

	bool dev_entered;



	if (psp->adev->no_hw_access)

		return 0;



	if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))

		return 0;

	dev_entered = drm_dev_enter(adev_to_drm(psp->adev), &idx);

	/*

	 * We allow sending PSP messages LOAD_ASD and UNLOAD_TA without acquiring

	 * a lock in drm_dev_enter during driver unload because we must call

	 * drm_dev_unplug as the beginning  of unload driver sequence . It is very

	 * crucial that userspace can't access device instances anymore.

	 */

	if (!dev_entered)

		WARN_ON(psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_LOAD_ASD &&

			psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_UNLOAD_TA);



	memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
@@ -676,6 +685,7 @@ psp_cmd_submit_buf(struct psp_context *psp, 
	}



exit:

	if (dev_entered)

		drm_dev_exit(idx);

	return ret;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+0 −2
Original line number Diff line number Diff line
@@ -983,11 +983,9 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v 
	if (offset == reg_access_ctrl->grbm_cntl) {

		/* if the target reg offset is grbm_cntl, write to scratch_reg2 */

		writel(v, scratch_reg2);

		writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));

	} else if (offset == reg_access_ctrl->grbm_idx) {

		/* if the target reg offset is grbm_idx, write to scratch_reg3 */

		writel(v, scratch_reg3);

		writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));

	} else {

		/*

		 * SCRATCH_REG0 	= read/write value