Unverified Commit 78c89aa3 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!14889 clk: ralink: mtmips: clock fixes for Ralink SoCs 

Merge Pull Request from: @ci-robot 
 
PR sync from: Tirui Yin <yintirui@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/B7NY3GDDOCXLU56DZGXUHA45M72ES2UV/ 
The following series contains two patches that address clock-related issues in the Ralink SoC family:

- The first patch introduces a missing 'periph' clock to the RT3883 SoC's clock plan. This corrects issues with peripherals such as UART, I2C, I2S, and UARTlite, which previously relied on an undefined 'periph' clock.
- The second patch ensures proper probe order of base clocks for older Ralink SoCs (RT2880, RT305x, and RT3883) by defining the 'xtal' clock first. This eliminates boot warnings and ensures that dependent clocks are set up correctly from the start.

Sergio Paracuellos (2):
  clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
  clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs


-- 
2.22.0
 
https://gitee.com/src-openeuler/kernel/issues/IBEAEQ 
 
Link:https://gitee.com/openeuler/kernel/pulls/14889

 

Reviewed-by: default avatarZhang Peng <zhangpeng362@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents fbb22bb9 ec115289

drivers/clk/ralink/clk-mtmips.c

+18 −8
Original line number Diff line number Diff line
@@ -263,8 +263,9 @@ static int mtmips_register_pherip_clocks(struct device_node *np, 
		.rate = _rate		 \

	}



static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {

	CLK_FIXED("xtal", NULL, 40000000)

static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {

	CLK_FIXED("xtal", NULL, 40000000),

	CLK_FIXED("periph", "xtal", 40000000)

};



static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
@@ -366,6 +367,12 @@ static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw) 
	return container_of(hw, struct mtmips_clk, hw);

}



static unsigned long rt2880_xtal_recalc_rate(struct clk_hw *hw,

					     unsigned long parent_rate)

{

	return 40000000;

}



static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,

					     unsigned long parent_rate)

{
@@ -677,10 +684,12 @@ static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw, 
}



static struct mtmips_clk rt2880_clks_base[] = {

	{ CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },

	{ CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }

};



static struct mtmips_clk rt305x_clks_base[] = {

	{ CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },

	{ CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }

};
@@ -690,6 +699,7 @@ static struct mtmips_clk rt3352_clks_base[] = { 
};



static struct mtmips_clk rt3883_clks_base[] = {

	{ CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },

	{ CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },

	{ CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }

};
@@ -746,8 +756,8 @@ static int mtmips_register_clocks(struct device_node *np, 
static const struct mtmips_clk_data rt2880_clk_data = {

	.clk_base = rt2880_clks_base,

	.num_clk_base = ARRAY_SIZE(rt2880_clks_base),

	.clk_fixed = rt305x_fixed_clocks,

	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),

	.clk_fixed = NULL,

	.num_clk_fixed = 0,

	.clk_factor = rt2880_factor_clocks,

	.num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),

	.clk_periph = rt2880_pherip_clks,
@@ -757,8 +767,8 @@ static const struct mtmips_clk_data rt2880_clk_data = { 
static const struct mtmips_clk_data rt305x_clk_data = {

	.clk_base = rt305x_clks_base,

	.num_clk_base = ARRAY_SIZE(rt305x_clks_base),

	.clk_fixed = rt305x_fixed_clocks,

	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),

	.clk_fixed = NULL,

	.num_clk_fixed = 0,

	.clk_factor = rt305x_factor_clocks,

	.num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),

	.clk_periph = rt305x_pherip_clks,
@@ -779,8 +789,8 @@ static const struct mtmips_clk_data rt3352_clk_data = { 
static const struct mtmips_clk_data rt3883_clk_data = {

	.clk_base = rt3883_clks_base,

	.num_clk_base = ARRAY_SIZE(rt3883_clks_base),

	.clk_fixed = rt305x_fixed_clocks,

	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),

	.clk_fixed = rt3883_fixed_clocks,

	.num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks),

	.clk_factor = NULL,

	.num_clk_factor = 0,

	.clk_periph = rt5350_pherip_clks,