Commit 78a90a1e authored by Sia Jee Heng's avatar Sia Jee Heng Committed by Vinod Koul
Browse files

dmaengine: dw-axi-dmac: Set constraint to the Max segment size 



Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.

Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.

Signed-off-by: default avatarSia Jee Heng <jee.heng.sia@intel.com>
Tested-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lore.kernel.org/r/20210125013255.25799-17-jee.heng.sia@intel.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent f74b3025

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

+8 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/device.h>

#include <linux/dmaengine.h>

#include <linux/dmapool.h>

#include <linux/dma-mapping.h>

#include <linux/err.h>

#include <linux/interrupt.h>

#include <linux/io.h>
@@ -1340,6 +1341,13 @@ static int dw_probe(struct platform_device *pdev) 
	dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;

	dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;



	/*

	 * Synopsis DesignWare AxiDMA datasheet mentioned Maximum

	 * supported blocks is 1024. Device register width is 4 bytes.

	 * Therefore, set constraint to 1024 * 4.

	 */

	dw->dma.dev->dma_parms = &dw->dma_parms;

	dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);

	platform_set_drvdata(pdev, chip);



	pm_runtime_enable(chip->dev);

drivers/dma/dw-axi-dmac/dw-axi-dmac.h

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ struct axi_dma_chan { 
struct dw_axi_dma {

	struct dma_device	dma;

	struct dw_axi_dma_hcfg	*hdata;

	struct device_dma_parameters	dma_parms;



	/* channels */

	struct axi_dma_chan	*chan;