staging: r8188eu: introduce new include dir for RTL8188eu driver (7884fc0a) · Commits · EulixOS / Software / Kernel

drivers/staging/r8188eu/include/Hal8188EPhyCfg.h

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		/******************************************************************************
		*
		* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of version 2 of the GNU General Public License as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful, but WITHOUT
		* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
		* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
		* more details.
		*
		* You should have received a copy of the GNU General Public License along with
		* this program; if not, write to the Free Software Foundation, Inc.,
		* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
		*
		*
		******************************************************************************/
		#ifndef __INC_HAL8188EPHYCFG_H__
		#define __INC_HAL8188EPHYCFG_H__

		/--------------------------Define Parameters-------------------------------/
		#define LOOP_LIMIT 5
		#define MAX_STALL_TIME 50 /* us */
		#define AntennaDiversityValue 0x80
		#define MAX_TXPWR_IDX_NMODE_92S 63
		#define Reset_Cnt_Limit 3

		#define IQK_MAC_REG_NUM 4
		#define IQK_ADDA_REG_NUM 16
		#define IQK_BB_REG_NUM 9
		#define HP_THERMAL_NUM 8

		#define MAX_AGGR_NUM 0x07

		/--------------------------Define Parameters-------------------------------/

		/------------------------------Define structure----------------------------/
		enum sw_chnl_cmd_id {
		CmdID_End,
		CmdID_SetTxPowerLevel,
		CmdID_BBRegWrite10,
		CmdID_WritePortUlong,
		CmdID_WritePortUshort,
		CmdID_WritePortUchar,
		CmdID_RF_WriteReg,
		};

		/* 1. Switch channel related */
		struct sw_chnl_cmd {
		enum sw_chnl_cmd_id CmdID;
		u32 Para1;
		u32 Para2;
		u32 msDelay;
		};

		enum hw90_block {
		HW90_BLOCK_MAC = 0,
		HW90_BLOCK_PHY0 = 1,
		HW90_BLOCK_PHY1 = 2,
		HW90_BLOCK_RF = 3,
		HW90_BLOCK_MAXIMUM = 4, /* Never use this */
		};

		enum rf_radio_path {
		RF_PATH_A = 0, /* Radio Path A */
		RF_PATH_B = 1, /* Radio Path B */
		RF_PATH_C = 2, /* Radio Path C */
		RF_PATH_D = 3, /* Radio Path D */
		};

		#define MAX_PG_GROUP 13

		#define RF_PATH_MAX 3
		#define MAX_TX_COUNT 4 /* path numbers */

		#define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */
		#define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8,
		*ch9~11, ch12~13, CH 14
		* total three groups */
		#define CHANNEL_GROUP_MAX_88E 6

		enum wireless_mode {
		WIRELESS_MODE_UNKNOWN = 0x00,
		WIRELESS_MODE_A = BIT2,
		WIRELESS_MODE_B = BIT0,
		WIRELESS_MODE_G = BIT1,
		WIRELESS_MODE_AUTO = BIT5,
		WIRELESS_MODE_N_24G = BIT3,
		WIRELESS_MODE_N_5G = BIT4,
		WIRELESS_MODE_AC = BIT6
		};

		enum phy_rate_tx_offset_area {
		RA_OFFSET_LEGACY_OFDM1,
		RA_OFFSET_LEGACY_OFDM2,
		RA_OFFSET_HT_OFDM1,
		RA_OFFSET_HT_OFDM2,
		RA_OFFSET_HT_OFDM3,
		RA_OFFSET_HT_OFDM4,
		RA_OFFSET_HT_CCK,
		};

		/* BB/RF related */
		enum RF_TYPE_8190P {
		RF_TYPE_MIN, /* 0 */
		RF_8225 = 1, /* 1 11b/g RF for verification only */
		RF_8256 = 2, /* 2 11b/g/n */
		RF_8258 = 3, /* 3 11a/b/g/n RF */
		RF_6052 = 4, /* 4 11b/g/n RF */
		/* TODO: We should remove this psudo PHY RF after we get new RF. */
		RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */
		};

		struct bb_reg_def {
		u32 rfintfs; /* set software control: */
		/* 0x870~0x877[8 bytes] */
		u32 rfintfi; /* readback data: */
		/* 0x8e0~0x8e7[8 bytes] */
		u32 rfintfo; /* output data: */
		/* 0x860~0x86f [16 bytes] */
		u32 rfintfe; /* output enable: */
		/* 0x860~0x86f [16 bytes] */
		u32 rf3wireOffset; /* LSSI data: */
		/* 0x840~0x84f [16 bytes] */
		u32 rfLSSI_Select; /* BB Band Select: */
		/* 0x878~0x87f [8 bytes] */
		u32 rfTxGainStage; /* Tx gain stage: */
		/* 0x80c~0x80f [4 bytes] */
		u32 rfHSSIPara1; /* wire parameter control1 : */
		/* 0x820~0x823,0x828~0x82b,
		* 0x830~0x833, 0x838~0x83b [16 bytes] */
		u32 rfHSSIPara2; /* wire parameter control2 : */
		/* 0x824~0x827,0x82c~0x82f, 0x834~0x837,
		* 0x83c~0x83f [16 bytes] */
		u32 rfSwitchControl; /* Tx Rx antenna control : */
		/* 0x858~0x85f [16 bytes] */
		u32 rfAGCControl1; /* AGC parameter control1 : */
		/* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
		* 0xc68~0xc6b [16 bytes] */
		u32 rfAGCControl2; /* AGC parameter control2 : */
		/* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
		* 0xc6c~0xc6f [16 bytes] */
		u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
		/* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
		* 0xc2c~0xc2f [16 bytes] */
		u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter,
		* Rx DC notch filter : */
		/* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
		* 0xc28~0xc2b [16 bytes] */
		u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
		/* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
		* 0xc98~0xc9b [16 bytes] */
		u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
		/* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
		* 0xc9c~0xc9f [16 bytes] */
		u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
		/* 0x8a0~0x8af [16 bytes] */
		u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for
		* Path A and B */
		};

		struct ant_sel_ofdm {
		u32 r_tx_antenna:4;
		u32 r_ant_l:4;
		u32 r_ant_non_ht:4;
		u32 r_ant_ht1:4;
		u32 r_ant_ht2:4;
		u32 r_ant_ht_s1:4;
		u32 r_ant_non_ht_s1:4;
		u32 OFDM_TXSC:2;
		u32 reserved:2;
		};

		struct ant_sel_cck {
		u8 r_cckrx_enable_2:2;
		u8 r_cckrx_enable:2;
		u8 r_ccktx_enable:4;
		};

		/------------------------------Define structure----------------------------/

		/------------------------Export global variable----------------------------/
		/------------------------Export global variable----------------------------/

		/------------------------Export Marco Definition---------------------------/
		/------------------------Export Marco Definition---------------------------/

		/--------------------------Exported Function prototype---------------------/
		/* */
		/* BB and RF register read/write */
		/* */
		u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask);
		void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr,
		u32 mask, u32 data);
		u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, enum rf_radio_path rfpath,
		u32 regaddr, u32 mask);
		void rtl8188e_PHY_SetRFReg(struct adapter *adapter, enum rf_radio_path rfpath,
		u32 regaddr, u32 mask, u32 data);

		/* Initialization related function */
		/* MAC/BB/RF HAL config */
		int PHY_MACConfig8188E(struct adapter *adapter);
		int PHY_BBConfig8188E(struct adapter *adapter);
		int PHY_RFConfig8188E(struct adapter *adapter);

		/* RF config */
		int rtl8188e_PHY_ConfigRFWithParaFile(struct adapter adapter, u8 filename,
		enum rf_radio_path rfpath);
		int rtl8188e_PHY_ConfigRFWithHeaderFile(struct adapter *adapter,
		enum rf_radio_path rfpath);

		/* Read initi reg value for tx power setting. */
		void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);

		/* BB TX Power R/W */
		void PHY_GetTxPowerLevel8188E(struct adapter adapter, u32 powerlevel);
		void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel);
		bool PHY_UpdateTxPowerDbm8188E(struct adapter *adapter, int power);

		void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);

		/* Switch bandwidth for 8192S */
		void PHY_SetBWMode8188E(struct adapter *adapter,
		enum ht_channel_width chnlwidth, unsigned char offset);

		/* channel switch related funciton */
		void PHY_SwChnl8188E(struct adapter *adapter, u8 channel);
		/* Call after initialization */
		void ChkFwCmdIoDone(struct adapter *adapter);

		/* BB/MAC/RF other monitor API */
		void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main);

		void PHY_SwitchEphyParameter(struct adapter *adapter);

		void PHY_EnableHostClkReq(struct adapter *adapter);

		bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);

		void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr,
		u32 mask, u32 data);
		/--------------------------Exported Function prototype---------------------/

		#define PHY_QueryBBReg(adapt, regaddr, mask) \
		rtl8188e_PHY_QueryBBReg((adapt), (regaddr), (mask))
		#define PHY_SetBBReg(adapt, regaddr, bitmask, data) \
		rtl8188e_PHY_SetBBReg((adapt), (regaddr), (bitmask), (data))
		#define PHY_QueryRFReg(adapt, rfpath, regaddr, bitmask) \
		rtl8188e_PHY_QueryRFReg((adapt), (rfpath), (regaddr), (bitmask))
		#define PHY_SetRFReg(adapt, rfpath, regaddr, bitmask, data) \
		rtl8188e_PHY_SetRFReg((adapt), (rfpath), (regaddr), (bitmask), (data))

		#define PHY_SetMacReg PHY_SetBBReg

		#define SIC_HW_SUPPORT 0

		#define SIC_MAX_POLL_CNT 5

		#define SIC_CMD_READY 0
		#define SIC_CMD_WRITE 1
		#define SIC_CMD_READ 2

		#define SIC_CMD_REG 0x1EB /* 1byte */
		#define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
		#define SIC_DATA_REG 0x1EC /* 1bc~1bf */

		#endif /* __INC_HAL8192CPHYCFG_H */

drivers/staging/r8188eu/include/Hal8188EPhyReg.h

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drivers/staging/r8188eu/include/Hal8188EPwrSeq.h

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		/******************************************************************************
		*
		* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of version 2 of the GNU General Public License as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful, but WITHOUT
		* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
		* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
		* more details.
		*
		* You should have received a copy of the GNU General Public License along with
		* this program; if not, write to the Free Software Foundation, Inc.,
		* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
		*
		*
		******************************************************************************/

		#ifndef __HAL8188EPWRSEQ_H__
		#define __HAL8188EPWRSEQ_H__

		#include "HalPwrSeqCmd.h"

		/*
		Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
		There are 6 HW Power States:
		0: POFF--Power Off
		1: PDN--Power Down
		2: CARDEMU--Card Emulation
		3: ACT--Active Mode
		4: LPS--Low Power State
		5: SUS--Suspend

		The transision from different states are defined below
		TRANS_CARDEMU_TO_ACT
		TRANS_ACT_TO_CARDEMU
		TRANS_CARDEMU_TO_SUS
		TRANS_SUS_TO_CARDEMU
		TRANS_CARDEMU_TO_PDN
		TRANS_ACT_TO_LPS
		TRANS_LPS_TO_ACT

		TRANS_END

		PWR SEQ Version: rtl8188E_PwrSeq_V09.h
		*/
		#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
		#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
		#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
		#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
		#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
		#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
		#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
		#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
		#define RTL8188E_TRANS_END_STEPS 1

		#define RTL8188E_TRANS_CARDEMU_TO_ACT \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here*/ \
		{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
		{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0\|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \
		{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /0x24[23] = 2b'01 schmit trigger / \
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4\|BIT3, 0}, /0x04[12:11] = 2b'00 disable WL suspend/ \
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /0x04[8] = 1 polling until return 0/ \
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, /wait till 0x04[8] = 0/ \
		{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /LDO normal mode/ \
		{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /SDIO Driving/ \

		#define RTL8188E_TRANS_ACT_TO_CARDEMU \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here*/ \
		{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/0x1F[7:0] = 0 turn off RF/ \
		{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /LDO Sleep mode/ \
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /0x04[9] = 1 turn off MAC by HW state machine/ \
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /wait till 0x04[9] = 0 polling until return 0 to disable/ \

		#define RTL8188E_TRANS_CARDEMU_TO_SUS \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here*/ \
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK\|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3\|BIT4, BIT3}, /0x04[12:11] = 2b'01enable WL suspend/ \
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3\|BIT4, BIT3\|BIT4}, /0x04[12:11] = 2b'11enable WL suspend for PCIe/ \
		{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK\|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
		{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK\|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /Clear SIC_EN register 0x40[12] = 1'b0 / \
		{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK\|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /Set USB suspend enable local register 0xfe10[4]=1 / \
		{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /Set SDIO suspend local register/ \
		{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /wait power state to suspend/

		#define RTL8188E_TRANS_SUS_TO_CARDEMU \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here*/ \
		{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /Set SDIO suspend local register/ \
		{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /wait power state to suspend/\
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3\|BIT4, 0}, /0x04[12:11] = 2b'01enable WL suspend/

		#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here*/ \
		{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /0x24[23] = 2b'01 schmit trigger / \
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK\|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3\|BIT4, BIT3}, /0x04[12:11] = 2b'01 enable WL suspend/ \
		{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK\|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
		{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK\|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /Clear SIC_EN register 0x40[12] = 1'b0 / \
		{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /Set USB suspend enable local register 0xfe10[4]=1 / \
		{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /Set SDIO suspend local register/ \
		{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /wait power state to suspend/

		#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here*/ \
		{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /Set SDIO suspend local register/ \
		{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /wait power state to suspend/\
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3\|BIT4, 0}, /0x04[12:11] = 2b'01enable WL suspend/

		#define RTL8188E_TRANS_CARDEMU_TO_PDN \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here*/ \
		{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/

		#define RTL8188E_TRANS_PDN_TO_CARDEMU \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here */ \
		{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/

		/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
		#define RTL8188E_TRANS_ACT_TO_LPS \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here */ \
		{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/Tx Pause/ \
		{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/Should be zero if no packet is transmitting/ \
		{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/Should be zero if no packet is transmitting/ \
		{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/Should be zero if no packet is transmitting/ \
		{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/Should be zero if no packet is transmitting/ \
		{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/CCK and OFDM are disabled,and clock are gated/ \
		{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/Delay 1us/ \
		{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/Reset MAC TRX/ \
		{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/check if removed later/ \
		{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/Respond TxOK to scheduler/ \

		#define RTL8188E_TRANS_LPS_TO_ACT \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here */ \
		{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /SDIO RPWM/\
		{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /USB RPWM/\
		{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /PCIe RPWM/\
		{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /Delay/\
		{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /. 0x08[4] = 0 switch TSF to 40M/\
		{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /Polling 0x109[7]=0 TSF in 40M/\
		{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6\|BIT7, 0}, /. 0x29[7:6] = 2b'00 enable BB clock/\
		{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /. 0x101[1] = 1/\
		{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /. 0x100[7:0] = 0xFF enable WMAC TRX/\
		{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1\|BIT0, BIT1\|BIT0}, /. 0x02[1:0] = 2b'11 enable BB macro/\
		{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /. 0x522 = 0/

		#define RTL8188E_TRANS_END \
		/* format */ \
		/* { offset, cut_msk, fab_msk\|interface_msk, base\|cmd, msk, value }, comments here*/ \
		{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0, PWR_CMD_END, 0, 0}, /* */

		extern struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
		extern struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS];
		extern struct wl_pwr_cfg rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
		extern struct wl_pwr_cfg rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
		extern struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
		extern struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
		extern struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
		extern struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
		extern struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];

		#endif /* __HAL8188EPWRSEQ_H__ */

drivers/staging/r8188eu/include/Hal8188ERateAdaptive.h

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		#ifndef __INC_RA_H
		#define __INC_RA_H
		/*++
		Copyright (c) Realtek Semiconductor Corp. All rights reserved.

		Module Name:
		RateAdaptive.h

		Abstract:
		Prototype of RA and related data structure.

		Major Change History:
		When Who What
		---------- --------------- -------------------------------
		2011-08-12 Page Create.
		--*/

		/* Rate adaptive define */
		#define PERENTRY 23
		#define RETRYSIZE 5
		#define RATESIZE 28
		#define TX_RPT2_ITEM_SIZE 8

		/* */
		/* TX report 2 format in Rx desc */
		/* */
		#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) \
		LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 9)
		#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) \
		LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 32)
		#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) \
		LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)

		#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) \
		LE_BITS_TO_4BYTE(__pAddr, 0, 16)
		#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) \
		LE_BITS_TO_1BYTE(__pAddr+2, 0, 8)
		#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) \
		LE_BITS_TO_1BYTE(__pAddr+3, 0, 8)
		#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) \
		LE_BITS_TO_1BYTE(__pAddr+4, 0, 8)
		#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) \
		LE_BITS_TO_1BYTE(__pAddr+4+1, 0, 8)
		#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) \
		LE_BITS_TO_1BYTE(__pAddr+4+2, 0, 8)
		#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) \
		LE_BITS_TO_1BYTE(__pAddr+4+3, 0, 8)

		/* End rate adaptive define */

		void ODM_RASupport_Init(struct odm_dm_struct *dm_odm);

		int ODM_RAInfo_Init_all(struct odm_dm_struct *dm_odm);

		int ODM_RAInfo_Init(struct odm_dm_struct *dm_odm, u8 MacID);

		u8 ODM_RA_GetShortGI_8188E(struct odm_dm_struct *dm_odm, u8 MacID);

		u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 MacID);

		u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 MacID);
		void ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct *dm_odm, u8 MacID,
		u8 RateID, u32 RateMask,
		u8 SGIEnable);

		void ODM_RA_SetRSSI_8188E(struct odm_dm_struct *dm_odm, u8 macid,
		u8 rssi);

		void ODM_RA_TxRPT2Handle_8188E(struct odm_dm_struct *dm_odm,
		u8 *txrpt_buf, u16 txrpt_len,
		u32 validentry0, u32 validentry1);

		void ODM_RA_Set_TxRPT_Time(struct odm_dm_struct *dm_odm, u16 minRptTime);

		#endif

drivers/staging/r8188eu/include/Hal8188EReg.h

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