Commit 78789705 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a779f0: Add WDT clock 



Add the module clock used by the RCLK Watchdog Timer (RWDT) on the
Renesas R-Car S4-8 (r8a779f0) SoC.  Mark it as a critical clock, to
ensure uninterrupted watchdog operation.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarGuenter Roeck <linux@roeck-us.net>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/8d9b280065a663f2cf31db7b21a010aa781a0af1.1642525158.git.geert+renesas@glider.be
parent 691419f9

drivers/clk/renesas/r8a779f0-cpg-mssr.c

+9 −0
Original line number Diff line number Diff line
@@ -121,6 +121,11 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("scif4",	705,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("wdt",		907,	R8A779F0_CLK_R),

};



static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {

	MOD_CLK_ID(907),	/* WDT */

};



/*
@@ -177,6 +182,10 @@ const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { 
	.num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks),

	.num_hw_mod_clks = 28 * 32,



	/* Critical Module Clocks */

	.crit_mod_clks = r8a779f0_crit_mod_clks,

	.num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks),



	/* Callbacks */

	.init = r8a779f0_cpg_mssr_init,

	.cpg_clk_register = rcar_gen4_cpg_clk_register,