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mainline inclusion from mainline-v6.11-rc1 commit f76a8420444beb1c3968504c8176a67d2d5fe18f category: feature bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IAGJQ7 CVE: NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f76a8420444beb1c3968504c8176a67d2d5fe18f ------------------------------------- The unit control RB tree has the unit control and unit ID information for all the PCI units. Use them to replace the box_ctls/pci_offsets to get an accurate unit control address for PCI uncore units. The UPI/M3UPI units in the discovery table are ignored. Please see the commit 65248a9a ("perf/x86/uncore: Add a quirk for UPI on SPR"). Manually allocate a unit control RB tree for UPI/M3UPI. Add cleanup_extra_boxes to release such manual allocation. Intel-SIG: commit f76a8420444b perf/x86/uncore: Apply the unit control RB tree to PCI uncore units Backport SPR/EMR CXL and HBM perfmon support to kernel v5.10 Signed-off-by:Kan Liang <kan.liang@linux.intel.com> Signed-off-by:
Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by:
Yunying Sun <yunying.sun@intel.com> Link: https://lore.kernel.org/r/20240614134631.1092359-7-kan.liang@linux.intel.com Signed-off-by:
Yunying Sun <yunying.sun@intel.com>