crypto: octeontx2 - add support to get engine capabilities (78506c2a) · Commits · EulixOS / Software / Kernel

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

+36 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,7 @@

		#define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF
		#define OTX2_CPT_NAME_LENGTH 64
		#define OTX2_CPT_DMA_MINALIGN 128

		#define BAD_OTX2_CPT_ENG_TYPE OTX2_CPT_MAX_ENG_TYPES

		@@ -32,6 +33,7 @@ enum otx2_cpt_eng_type {

		/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
		#define MBOX_MSG_GET_ENG_GRP_NUM 0xBFF
		#define MBOX_MSG_GET_CAPS 0xBFD

		/*
		* Message request and response to get engine group number
		@@ -49,6 +51,40 @@ struct otx2_cpt_egrp_num_rsp {
		u8 eng_grp_num;
		};

		/* CPT HW capabilities */
		union otx2_cpt_eng_caps {
		u64 u;
		struct {
		u64 reserved_0_4:5;
		u64 mul:1;
		u64 sha1_sha2:1;
		u64 chacha20:1;
		u64 zuc_snow3g:1;
		u64 sha3:1;
		u64 aes:1;
		u64 kasumi:1;
		u64 des:1;
		u64 crc:1;
		u64 reserved_14_63:50;
		};
		};

		/*
		* Message request and response to get HW capabilities for each
		* engine type (SE, IE, AE).
		* This messages are only used between CPT PF <=> CPT VF
		*/
		struct otx2_cpt_caps_msg {
		struct mbox_msghdr hdr;
		};

		struct otx2_cpt_caps_rsp {
		struct mbox_msghdr hdr;
		u16 cpt_pf_drv_version;
		u8 cpt_revision;
		union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
		};

		static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot,
		u64 offs, u64 val)
		{

drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h

0 → 100644

+51 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only
		* Copyright (C) 2020 Marvell.
		*/

		#ifndef __OTX2_CPT_REQMGR_H
		#define __OTX2_CPT_REQMGR_H

		#include "otx2_cpt_common.h"

		/* Completion code size and initial value */
		#define OTX2_CPT_COMPLETION_CODE_SIZE 8
		#define OTX2_CPT_COMPLETION_CODE_INIT OTX2_CPT_COMP_E_NOTDONE

		union otx2_cpt_opcode {
		u16 flags;
		struct {
		u8 major;
		u8 minor;
		} s;
		};

		/*
		* CPT_INST_S software command definitions
		* Words EI (0-3)
		*/
		union otx2_cpt_iq_cmd_word0 {
		u64 u;
		struct {
		__be16 opcode;
		__be16 param1;
		__be16 param2;
		__be16 dlen;
		} s;
		};

		union otx2_cpt_iq_cmd_word3 {
		u64 u;
		struct {
		u64 cptr:61;
		u64 grp:3;
		} s;
		};

		struct otx2_cpt_iq_command {
		union otx2_cpt_iq_cmd_word0 cmd;
		u64 dptr;
		u64 rptr;
		union otx2_cpt_iq_cmd_word3 cptr;
		};

		#endif /* __OTX2_CPT_REQMGR_H */

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

+62 −0

Original line number	Diff line number	Diff line
		@@ -4,9 +4,11 @@
		#ifndef __OTX2_CPTLF_H
		#define __OTX2_CPTLF_H

		#include <linux/soc/marvell/octeontx2/asm.h>
		#include <mbox.h>
		#include <rvu.h>
		#include "otx2_cpt_common.h"
		#include "otx2_cpt_reqmgr.h"

		/*
		* CPT instruction and pending queues user requested length in CPT_INST_S msgs
		@@ -272,6 +274,66 @@ static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs)
		}
		}

		static inline void otx2_cpt_fill_inst(union otx2_cpt_inst_s *cptinst,
		struct otx2_cpt_iq_command *iq_cmd,
		u64 comp_baddr)
		{
		cptinst->u[0] = 0x0;
		cptinst->s.doneint = true;
		cptinst->s.res_addr = comp_baddr;
		cptinst->u[2] = 0x0;
		cptinst->u[3] = 0x0;
		cptinst->s.ei0 = iq_cmd->cmd.u;
		cptinst->s.ei1 = iq_cmd->dptr;
		cptinst->s.ei2 = iq_cmd->rptr;
		cptinst->s.ei3 = iq_cmd->cptr.u;
		}

		/*
		* On OcteonTX2 platform the parameter insts_num is used as a count of
		* instructions to be enqueued. The valid values for insts_num are:
		* 1 - 1 CPT instruction will be enqueued during LMTST operation
		* 2 - 2 CPT instructions will be enqueued during LMTST operation
		*/
		static inline void otx2_cpt_send_cmd(union otx2_cpt_inst_s *cptinst,
		u32 insts_num, struct otx2_cptlf_info *lf)
		{
		void __iomem *lmtline = lf->lmtline;
		long ret;

		/*
		* Make sure memory areas pointed in CPT_INST_S
		* are flushed before the instruction is sent to CPT
		*/
		dma_wmb();

		do {
		/* Copy CPT command to LMTLINE */
		memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);

		/*
		* LDEOR initiates atomic transfer to I/O device
		* The following will cause the LMTST to fail (the LDEOR
		* returns zero):
		* - No stores have been performed to the LMTLINE since it was
		* last invalidated.
		* - The bytes which have been stored to LMTLINE since it was
		* last invalidated form a pattern that is non-contiguous, does
		* not start at byte 0, or does not end on a 8-byte boundary.
		* (i.e.comprises a formation of other than 1–16 8-byte
		* words.)
		*
		* These rules are designed such that an operating system
		* context switch or hypervisor guest switch need have no
		* knowledge of the LMTST operations; the switch code does not
		* need to store to LMTCANCEL. Also note as LMTLINE data cannot
		* be read, there is no information leakage between processes.
		*/
		ret = otx2_lmt_flush(lf->ioreg);

		} while (!ret);
		}

		int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,
		int lfs_num);
		void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -31,6 +31,9 @@ struct otx2_cptpf_dev {
		struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM];
		struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */
		struct otx2_cptlfs_info lfs; /* CPT LFs attached to this PF */
		/* HW capabilities for each engine type */
		union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
		bool is_eng_caps_discovered;

		/* AF <=> PF mbox */
		struct otx2_mbox afpf_mbox;

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -500,6 +500,11 @@ static int cptpf_sriov_enable(struct pci_dev *pdev, int num_vfs)
		if (ret)
		goto destroy_flr;

		/* Get CPT HW capabilities using LOAD_FVC operation. */
		ret = otx2_cpt_discover_eng_capabilities(cptpf);
		if (ret)
		goto disable_intr;

		ret = otx2_cpt_create_eng_grps(cptpf->pdev, &cptpf->eng_grps);
		if (ret)
		goto disable_intr;