Commit 77f6da90 authored by Vinod Koul's avatar Vinod Koul Committed by Dmitry Baryshkov
Browse files

drm/msm/disp/dpu1: Add DSC support in hw_ctl 



Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/480918/
Link: https://lore.kernel.org/r/20220406094031.1027376-7-vkoul@kernel.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 7c5ab05e

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+10 −1
Original line number Diff line number Diff line
@@ -25,6 +25,8 @@ 
#define   CTL_MERGE_3D_ACTIVE           0x0E4

#define   CTL_INTF_ACTIVE               0x0F4

#define   CTL_MERGE_3D_FLUSH            0x100

#define   CTL_DSC_ACTIVE                0x0E8

#define   CTL_DSC_FLUSH                0x104

#define   CTL_INTF_FLUSH                0x110

#define   CTL_INTF_MASTER               0x134

#define   CTL_FETCH_PIPE_ACTIVE         0x0FC
@@ -34,6 +36,7 @@ 


#define DPU_REG_RESET_TIMEOUT_US        2000

#define  MERGE_3D_IDX   23

#define  DSC_IDX        22

#define  INTF_IDX       31

#define CTL_INVALID_BIT                 0xffff

#define CTL_DEFAULT_GROUP_ID		0xf
@@ -126,7 +129,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) 


static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)

{



	if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))

		DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,

				ctx->pending_merge_3d_flush_mask);
@@ -511,6 +513,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, 
	if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))

		mode_sel = CTL_DEFAULT_GROUP_ID  << 28;



	if (cfg->dsc)

		DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);



	if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)

		mode_sel |= BIT(17);
@@ -522,6 +527,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, 
	if (cfg->merge_3d)

		DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,

			      BIT(cfg->merge_3d - MERGE_3D_0));

	if (cfg->dsc) {

		DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX);

		DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);

	}

}



static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg { 
 * @merge_3d:              3d merge block used

 * @intf_mode_sel:         Interface mode, cmd / vid

 * @stream_sel:            Stream selection for multi-stream interfaces

 * @dsc:                   DSC BIT masks used

 */

struct dpu_hw_intf_cfg {

	enum dpu_intf intf;
@@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg { 
	enum dpu_merge_3d merge_3d;

	enum dpu_ctl_mode_sel intf_mode_sel;

	int stream_sel;

	unsigned int dsc;

};



/**