Commit 77c12bf3 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'gpio-fixes-for-v5.10-rc7' of... 

Merge tag 'gpio-fixes-for-v5.10-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into fixes

gpio fixes for v5.10-rc7

- disable pm_runtime in error path in gpio-arizona
- fix a NULL pointer dereference in gpio-dwapb
- fix a resource leak in gpio-zynq
- balance the freeing of pinctrl ranges if PINCTRL is not selected
- fix a potential use-after-free error in gpio-mvebu
parents b6505459 7ee1a01e

drivers/gpio/gpio-arizona.c

+1 −0
Original line number Diff line number Diff line
@@ -192,6 +192,7 @@ static int arizona_gpio_probe(struct platform_device *pdev) 
	ret = devm_gpiochip_add_data(&pdev->dev, &arizona_gpio->gpio_chip,

				     arizona_gpio);

	if (ret < 0) {

		pm_runtime_disable(&pdev->dev);

		dev_err(&pdev->dev, "Could not register gpiochip, %d\n",

			ret);

		return ret;

drivers/gpio/gpio-dwapb.c

+2 −0
Original line number Diff line number Diff line
@@ -724,6 +724,8 @@ static int dwapb_gpio_probe(struct platform_device *pdev) 
			return err;

	}



	platform_set_drvdata(pdev, gpio);



	return 0;

}

drivers/gpio/gpio-mvebu.c

+11 −5
Original line number Diff line number Diff line
@@ -1197,6 +1197,13 @@ static int mvebu_gpio_probe(struct platform_device *pdev) 


	devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);



	/* Some MVEBU SoCs have simple PWM support for GPIO lines */

	if (IS_ENABLED(CONFIG_PWM)) {

		err = mvebu_pwm_probe(pdev, mvchip, id);

		if (err)

			return err;

	}



	/* Some gpio controllers do not provide irq support */

	if (!have_irqs)

		return 0;
@@ -1206,7 +1213,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev) 
	if (!mvchip->domain) {

		dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",

			mvchip->chip.label);

		return -ENODEV;

		err = -ENODEV;

		goto err_pwm;

	}



	err = irq_alloc_domain_generic_chips(
@@ -1254,14 +1262,12 @@ static int mvebu_gpio_probe(struct platform_device *pdev) 
						 mvchip);

	}



	/* Some MVEBU SoCs have simple PWM support for GPIO lines */

	if (IS_ENABLED(CONFIG_PWM))

		return mvebu_pwm_probe(pdev, mvchip, id);



	return 0;



err_domain:

	irq_domain_remove(mvchip->domain);

err_pwm:

	pwmchip_remove(&mvchip->mvpwm->chip);



	return err;

}

drivers/gpio/gpio-zynq.c

+2 −2
Original line number Diff line number Diff line
@@ -574,7 +574,7 @@ static int zynq_gpio_irq_reqres(struct irq_data *d) 
	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);

	int ret;



	ret = pm_runtime_get_sync(chip->parent);

	ret = pm_runtime_resume_and_get(chip->parent);

	if (ret < 0)

		return ret;
@@ -942,7 +942,7 @@ static int zynq_gpio_probe(struct platform_device *pdev) 


	pm_runtime_set_active(&pdev->dev);

	pm_runtime_enable(&pdev->dev);

	ret = pm_runtime_get_sync(&pdev->dev);

	ret = pm_runtime_resume_and_get(&pdev->dev);

	if (ret < 0)

		goto err_pm_dis;

drivers/gpio/gpiolib.c

+5 −0
Original line number Diff line number Diff line
@@ -1806,6 +1806,11 @@ EXPORT_SYMBOL_GPL(gpiochip_generic_request); 
 */

void gpiochip_generic_free(struct gpio_chip *gc, unsigned offset)

{

#ifdef CONFIG_PINCTRL

	if (list_empty(&gc->gpiodev->pin_ranges))

		return;

#endif



	pinctrl_gpio_free(gc->gpiodev->base + offset);

}

EXPORT_SYMBOL_GPL(gpiochip_generic_free);