Commit 77b6f79d authored by John Harrison's avatar John Harrison
Browse files

drm/i915/guc: Update to GuC version 69.0.3 



Update to the latest GuC release.

The latest GuC firmware introduces a number of interface changes:

GuC may return NO_RESPONSE_RETRY message for requests sent over CTB.
Add support for this reply and try resending the request again as a
new CTB message.

A KLV (key-length-value) mechanism is now used for passing
configuration data such as CTB management.

With the new KLV scheme, the old CTB management actions are no longer
used and are removed.

Register capture on hang is now supported by GuC. Full i915 support
for this will be added by a later patch. A minimum support of
providing capture memory and register lists is required though, so add
that in.

The device id of the current platform needs to be provided at init time.

The 'poll CS' w/a (Wa_22012773006) was blanket enabled by previous
versions of GuC. It must now be explicitly requested by the KMD. So,
add in the code to turn it on when relevant.

The GuC log entry format has changed. This requires adding a new field
to the log header structure to mark the wrap point at the end of the
buffer (as the buffer size is no longer a multiple of the log entry
size).

New CTB notification messages are now sent for some things that were
previously only sent via MMIO notifications.

Of these, the crash dump notification was not really being handled by
i915. It called the log flush code but that only flushed the regular
debug log and then only if relay logging was enabled. So just report
an error message instead.

The 'exception' notification was just being ignored completely. So add
an error message for that as well.

Note that in either the crash dump or the exception case, the GuC is
basically dead. The KMD will detect this via the heartbeat and trigger
both an error log (which will include the crash dump as part of the
GuC log) and a GT reset. So no other processing is really required.

Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220107000622.292081-3-John.C.Harrison@Intel.com
parent 53c8283b

Documentation/gpu/i915.rst

+1 −0
Original line number Diff line number Diff line
@@ -539,6 +539,7 @@ GuC ABI 
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h

.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h

.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h



HuC

---

drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

+38 −42
Original line number Diff line number Diff line
@@ -7,9 +7,9 @@ 
#define _ABI_GUC_ACTIONS_ABI_H



/**

 * DOC: HOST2GUC_REGISTER_CTB

 * DOC: HOST2GUC_SELF_CFG

 *

 * This message is used as part of the `CTB based communication`_ setup.

 * This message is used by Host KMD to setup of the `GuC Self Config KLVs`_.

 *

 * This message must be sent as `MMIO HXG Message`_.

 *
@@ -22,20 +22,18 @@ 
 *  |   +-------+--------------------------------------------------------------+

 *  |   | 27:16 | DATA0 = MBZ                                                  |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_REGISTER_CTB` = 0x4505        |

 *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508            |

 *  +---+-------+--------------------------------------------------------------+

 *  | 1 | 31:12 | RESERVED = MBZ                                               |

 *  | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_           |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  11:8 | **TYPE** - type for the `CT Buffer`_                         |

 *  |   |  15:0 | **KLV_LEN** - KLV length                                     |

 *  |   |       |                                                              |

 *  |   |       |   - _`GUC_CTB_TYPE_HOST2GUC` = 0                             |

 *  |   |       |   - _`GUC_CTB_TYPE_GUC2HOST` = 1                             |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |   7:0 | **SIZE** - size of the `CT Buffer`_ in 4K units minus 1      |

 *  |   |       |   - 32 bit KLV = 1                                           |

 *  |   |       |   - 64 bit KLV = 2                                           |

 *  +---+-------+--------------------------------------------------------------+

 *  | 2 |  31:0 | **DESC_ADDR** - GGTT address of the `CTB Descriptor`_        |

 *  | 2 |  31:0 | **VALUE32** - Bits 31-0 of the KLV value                     |

 *  +---+-------+--------------------------------------------------------------+

 *  | 3 |  31:0 | **BUFF_ADDF** - GGTT address of the `CT Buffer`_             |

 *  | 3 |  31:0 | **VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2)  |

 *  +---+-------+--------------------------------------------------------------+

 *

 *  +---+-------+--------------------------------------------------------------+
@@ -45,28 +43,25 @@ 
 *  |   +-------+--------------------------------------------------------------+

 *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  27:0 | DATA0 = MBZ                                                  |

 *  |   |  27:0 | DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognized   |

 *  +---+-------+--------------------------------------------------------------+

 */

#define GUC_ACTION_HOST2GUC_REGISTER_CTB		0x4505

#define GUC_ACTION_HOST2GUC_SELF_CFG			0x0508



#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_MBZ		(0xfffff << 12)

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_TYPE	(0xf << 8)

#define   GUC_CTB_TYPE_HOST2GUC				0u

#define   GUC_CTB_TYPE_GUC2HOST				1u

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_SIZE	(0xff << 0)

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_2_DESC_ADDR	GUC_HXG_REQUEST_MSG_n_DATAn

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_3_BUFF_ADDR	GUC_HXG_REQUEST_MSG_n_DATAn

#define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0

#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY		(0xffff << 16)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN		(0xffff << 0)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32		GUC_HXG_REQUEST_MSG_n_DATAn

#define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64		GUC_HXG_REQUEST_MSG_n_DATAn



#define HOST2GUC_REGISTER_CTB_RESPONSE_MSG_LEN		GUC_HXG_RESPONSE_MSG_MIN_LEN

#define HOST2GUC_REGISTER_CTB_RESPONSE_MSG_0_MBZ	GUC_HXG_RESPONSE_MSG_0_DATA0

#define HOST2GUC_SELF_CFG_RESPONSE_MSG_LEN		GUC_HXG_RESPONSE_MSG_MIN_LEN

#define HOST2GUC_SELF_CFG_RESPONSE_MSG_0_NUM		GUC_HXG_RESPONSE_MSG_0_DATA0



/**

 * DOC: HOST2GUC_DEREGISTER_CTB

 * DOC: HOST2GUC_CONTROL_CTB

 *

 * This message is used as part of the `CTB based communication`_ teardown.

 * This H2G action allows Vf Host to enable or disable H2G and G2H `CT Buffer`_.

 *

 * This message must be sent as `MMIO HXG Message`_.

 *
@@ -79,15 +74,12 @@ 
 *  |   +-------+--------------------------------------------------------------+

 *  |   | 27:16 | DATA0 = MBZ                                                  |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_DEREGISTER_CTB` = 0x4506      |

 *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509         |

 *  +---+-------+--------------------------------------------------------------+

 *  | 1 | 31:12 | RESERVED = MBZ                                               |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  11:8 | **TYPE** - type of the `CT Buffer`_                          |

 *  | 1 |  31:0 | **CONTROL** - control `CTB based communication`_             |

 *  |   |       |                                                              |

 *  |   |       | see `GUC_ACTION_HOST2GUC_REGISTER_CTB`_                      |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |   7:0 | RESERVED = MBZ                                               |

 *  |   |       |   - _`GUC_CTB_CONTROL_DISABLE` = 0                           |

 *  |   |       |   - _`GUC_CTB_CONTROL_ENABLE` = 1                            |

 *  +---+-------+--------------------------------------------------------------+

 *

 *  +---+-------+--------------------------------------------------------------+
@@ -100,16 +92,16 @@ 
 *  |   |  27:0 | DATA0 = MBZ                                                  |

 *  +---+-------+--------------------------------------------------------------+

 */

#define GUC_ACTION_HOST2GUC_DEREGISTER_CTB		0x4506

#define GUC_ACTION_HOST2GUC_CONTROL_CTB			0x4509



#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)

#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_0_MBZ	GUC_HXG_REQUEST_MSG_0_DATA0

#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_1_MBZ	(0xfffff << 12)

#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_1_TYPE	(0xf << 8)

#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_1_MBZ2	(0xff << 0)

#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)

#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0

#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_1_CONTROL	GUC_HXG_REQUEST_MSG_n_DATAn

#define   GUC_CTB_CONTROL_DISABLE			0u

#define   GUC_CTB_CONTROL_ENABLE			1u



#define HOST2GUC_DEREGISTER_CTB_RESPONSE_MSG_LEN	GUC_HXG_RESPONSE_MSG_MIN_LEN

#define HOST2GUC_DEREGISTER_CTB_RESPONSE_MSG_0_MBZ	GUC_HXG_RESPONSE_MSG_0_DATA0

#define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_LEN		GUC_HXG_RESPONSE_MSG_MIN_LEN

#define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_0_MBZ		GUC_HXG_RESPONSE_MSG_0_DATA0



/* legacy definitions */
@@ -143,8 +135,12 @@ enum intel_guc_action { 
	INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,

	INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,

	INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,

	INTEL_GUC_ACTION_RESET_CLIENT = 0x5507,

	INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,

	INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,

	INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,

	INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,

	INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,

	INTEL_GUC_ACTION_NOTIFY_EXCEPTION = 0x8005,

	INTEL_GUC_ACTION_LIMIT

};

drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h

0 → 100644
+82 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2021 Intel Corporation

 */



#ifndef _ABI_GUC_KLVS_ABI_H

#define _ABI_GUC_KLVS_ABI_H



/**

 * DOC: GuC KLV

 *

 *  +---+-------+--------------------------------------------------------------+

 *  |   | Bits  | Description                                                  |

 *  +===+=======+==============================================================+

 *  | 0 | 31:16 | **KEY** - KLV key identifier                                 |

 *  |   |       |   - `GuC Self Config KLVs`_                                  |

 *  |   |       |                                                              |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  15:0 | **LEN** - length of VALUE (in 32bit dwords)                  |

 *  +---+-------+--------------------------------------------------------------+

 *  | 1 |  31:0 | **VALUE** - actual value of the KLV (format depends on KEY)  |

 *  +---+-------+                                                              |

 *  |...|       |                                                              |

 *  +---+-------+                                                              |

 *  | n |  31:0 |                                                              |

 *  +---+-------+--------------------------------------------------------------+

 */



#define GUC_KLV_LEN_MIN				1u

#define GUC_KLV_0_KEY				(0xffff << 16)

#define GUC_KLV_0_LEN				(0xffff << 0)

#define GUC_KLV_n_VALUE				(0xffffffff << 0)



/**

 * DOC: GuC Self Config KLVs

 *

 * `GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_.

 *

 * _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902

 *      Refers to 64 bit Global Gfx address of H2G `CT Buffer`_.

 *      Should be above WOPCM address but below APIC base address for native mode.

 *

 * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR` : 0x0903

 *      Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_.

 *      Should be above WOPCM address but below APIC base address for native mode.

 *

 * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE` : 0x0904

 *      Refers to size of H2G `CT Buffer`_ in bytes.

 *      Should be a multiple of 4K.

 *

 * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR` : 0x0905

 *      Refers to 64 bit Global Gfx address of G2H `CT Buffer`_.

 *      Should be above WOPCM address but below APIC base address for native mode.

 *

 * _`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR` : 0x0906

 *      Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_.

 *      Should be above WOPCM address but below APIC base address for native mode.

 *

 * _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE` : 0x0907

 *      Refers to size of G2H `CT Buffer`_ in bytes.

 *      Should be a multiple of 4K.

 */



#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_KEY		0x0902

#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_LEN		2u



#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_KEY	0x0903

#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_LEN	2u



#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_KEY		0x0904

#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_LEN		1u



#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_KEY		0x0905

#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_LEN		2u



#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_KEY	0x0906

#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_LEN	2u



#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY		0x0907

#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN		1u



#endif /* _ABI_GUC_KLVS_ABI_H */

drivers/gpu/drm/i915/gt/uc/intel_guc.c

+109 −17
Original line number Diff line number Diff line
@@ -182,6 +182,9 @@ void intel_guc_init_early(struct intel_guc *guc) 
		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;

		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);

	}



	intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_EXCEPTION |

				  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);

}



void intel_guc_init_late(struct intel_guc *guc)
@@ -222,32 +225,48 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) 
	u32 flags;



	#if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)

	#define UNIT SZ_1M

	#define FLAG GUC_LOG_ALLOC_IN_MEGABYTE

	#define LOG_UNIT SZ_1M

	#define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS

	#else

	#define UNIT SZ_4K

	#define FLAG 0

	#define LOG_UNIT SZ_4K

	#define LOG_FLAG 0

	#endif



	#if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0)

	#define CAPTURE_UNIT SZ_1M

	#define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS

	#else

	#define CAPTURE_UNIT SZ_4K

	#define CAPTURE_FLAG 0

	#endif



	BUILD_BUG_ON(!CRASH_BUFFER_SIZE);

	BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT));

	BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT));

	BUILD_BUG_ON(!DEBUG_BUFFER_SIZE);

	BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, UNIT));

	BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT));

	BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE);

	BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT));



	BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) >

	BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) >

			(GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));

	BUILD_BUG_ON((DEBUG_BUFFER_SIZE / UNIT - 1) >

	BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) >

			(GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT));

	BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) >

			(GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT));



	flags = GUC_LOG_VALID |

		GUC_LOG_NOTIFY_ON_HALF_FULL |

		FLAG |

		((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) |

		((DEBUG_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DEBUG_SHIFT) |

		CAPTURE_FLAG |

		LOG_FLAG |

		((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) |

		((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) |

		((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) << GUC_LOG_CAPTURE_SHIFT) |

		(offset << GUC_LOG_BUF_ADDR_SHIFT);



	#undef UNIT

	#undef FLAG

	#undef LOG_UNIT

	#undef LOG_FLAG

	#undef CAPTURE_UNIT

	#undef CAPTURE_FLAG



	return flags;

}
@@ -260,6 +279,26 @@ static u32 guc_ctl_ads_flags(struct intel_guc *guc) 
	return flags;

}



static u32 guc_ctl_wa_flags(struct intel_guc *guc)

{

	struct intel_gt *gt = guc_to_gt(guc);

	u32 flags = 0;



	/* Wa_22012773006:gen11,gen12 < XeHP */

	if (GRAPHICS_VER(gt->i915) >= 11 &&

	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))

		flags |= GUC_WA_POLLCS;



	return flags;

}



static u32 guc_ctl_devid(struct intel_guc *guc)

{

	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;



	return (INTEL_DEVID(i915) << 16) | INTEL_REVID(i915);

}



/*

 * Initialise the GuC parameter block before starting the firmware

 * transfer. These parameters are read by the firmware on startup
@@ -276,6 +315,8 @@ static void guc_init_params(struct intel_guc *guc) 
	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);

	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);

	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);

	params[GUC_CTL_WA] = guc_ctl_wa_flags(guc);

	params[GUC_CTL_DEVID] = guc_ctl_devid(guc);



	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)

		DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
@@ -513,9 +554,10 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, 
	/* Make sure to handle only enabled messages */

	msg = payload[0] & guc->msg_enabled_mask;



	if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |

		   INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))

		intel_guc_log_handle_flush_event(&guc->log);

	if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)

		drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n");

	if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)

		drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n");



	return 0;

}
@@ -549,7 +591,7 @@ int intel_guc_suspend(struct intel_guc *guc) 
{

	int ret;

	u32 action[] = {

		INTEL_GUC_ACTION_RESET_CLIENT,

		INTEL_GUC_ACTION_CLIENT_SOFT_RESET,

	};



	if (!intel_guc_is_ready(guc))
@@ -713,6 +755,56 @@ int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size, 
	return 0;

}



static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)

{

	u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = {

		FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |

		FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |

		FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, GUC_ACTION_HOST2GUC_SELF_CFG),

		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) |

		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len),

		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, lower_32_bits(value)),

		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, upper_32_bits(value)),

	};

	int ret;



	GEM_BUG_ON(len > 2);

	GEM_BUG_ON(len == 1 && upper_32_bits(value));



	/* Self config must go over MMIO */

	ret = intel_guc_send_mmio(guc, request, ARRAY_SIZE(request), NULL, 0);



	if (unlikely(ret < 0))

		return ret;

	if (unlikely(ret > 1))

		return -EPROTO;

	if (unlikely(!ret))

		return -ENOKEY;



	return 0;

}



static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)

{

	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;

	int err = __guc_action_self_cfg(guc, key, len, value);



	if (unlikely(err))

		i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",

				 ERR_PTR(err), key, value);

	return err;

}



int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value)

{

	return __guc_self_cfg(guc, key, 1, value);

}



int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value)

{

	return __guc_self_cfg(guc, key, 2, value);

}



/**

 * intel_guc_load_status - dump information about GuC load status

 * @guc: the GuC

drivers/gpu/drm/i915/gt/uc/intel_guc.h

+4 −0
Original line number Diff line number Diff line
@@ -328,6 +328,8 @@ int intel_guc_resume(struct intel_guc *guc); 
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);

int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,

				   struct i915_vma **out_vma, void **out_vaddr);

int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value);

int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value);



static inline bool intel_guc_is_supported(struct intel_guc *guc)

{
@@ -404,6 +406,8 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc, 
					const u32 *msg, u32 len);

int intel_guc_engine_failure_process_msg(struct intel_guc *guc,

					 const u32 *msg, u32 len);

int intel_guc_error_capture_process_msg(struct intel_guc *guc,

					const u32 *msg, u32 len);



void intel_guc_find_hung_context(struct intel_engine_cs *engine);