Commit 77b0ddb4 authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV_MWR 



i.MX8MP HDMI supports HDCP and HRV_MWR(HDMI RX Video Memory Write Master
for RXRX validation), so add them.

Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 50299fa1

drivers/soc/imx/imx8mp-blk-ctrl.c

+30 −0
Original line number Original line Diff line number Diff line
@@ -235,6 +235,13 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc, 
		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));

		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));

		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));

		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));

		break;

		break;

	case IMX8MP_HDMIBLK_PD_HDCP:

		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));

		break;

	case IMX8MP_HDMIBLK_PD_HRV:

		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));

		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));

		break;

	default:

	default:

		break;

		break;

	}

	}
@@ -283,6 +290,13 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc, 
		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));

		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));

		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));

		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));

		break;

		break;

	case IMX8MP_HDMIBLK_PD_HDCP:

		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));

		break;

	case IMX8MP_HDMIBLK_PD_HRV:

		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));

		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));

		break;

	default:

	default:

		break;

		break;

	}

	}
@@ -365,6 +379,22 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = { 
		.num_clks = 2,

		.num_clks = 2,

		.gpc_name = "hdmi-tx-phy",

		.gpc_name = "hdmi-tx-phy",

	},

	},

	[IMX8MP_HDMIBLK_PD_HRV] = {

		.name = "hdmiblk-hrv",

		.clk_names = (const char *[]){ "axi", "apb" },

		.num_clks = 2,

		.gpc_name = "hrv",

		.path_names = (const char *[]){"hrv"},

		.num_paths = 1,

	},

	[IMX8MP_HDMIBLK_PD_HDCP] = {

		.name = "hdmiblk-hdcp",

		.clk_names = (const char *[]){ "axi", "apb" },

		.num_clks = 2,

		.gpc_name = "hdcp",

		.path_names = (const char *[]){"hdcp"},

		.num_paths = 1,

	},

};

};





static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {

static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {