Commit 776e49af authored by Mark Rutland's avatar Mark Rutland Committed by Catalin Marinas
Browse files

arm64: setup: name `mair` register 



In __cpu_setup we conditionally manipulate the MAIR_EL1 value in x5
before later reusing x5 as a scratch register for unrelated temporary
variables.

To make this a bit clearer, let's move the MAIR_EL1 value into a named
register `mair`. To simplify the register allocation, this is placed in
the highest available caller-saved scratch register, x17. As it is no
longer clobbered by other usage, we can write the value to MAIR_EL1 at
the end of the function as we do for TCR_EL1 rather than part-way though
feature discovery.

There should be no functional change as as a result of this patch.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210326180137.43119-2-mark.rutland@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent b07f3499

arch/arm64/mm/proc.S

+6 −3
Original line number Diff line number Diff line
@@ -421,7 +421,8 @@ SYM_FUNC_START(__cpu_setup) 
	/*

	 * Memory region attributes

	 */

	mov_q	x5, MAIR_EL1_SET

	mair	.req	x17

	mov_q	mair, MAIR_EL1_SET

#ifdef CONFIG_ARM64_MTE

	mte_tcr	.req	x20
@@ -438,7 +439,7 @@ SYM_FUNC_START(__cpu_setup) 


	/* Normal Tagged memory type at the corresponding MAIR index */

	mov	x10, #MAIR_ATTR_NORMAL_TAGGED

	bfi	x5, x10, #(8 *  MT_NORMAL_TAGGED), #8

	bfi	mair, x10, #(8 *  MT_NORMAL_TAGGED), #8



	/* initialize GCR_EL1: all non-zero tags excluded by default */

	mov	x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK)
@@ -452,7 +453,6 @@ SYM_FUNC_START(__cpu_setup) 
	mov_q	mte_tcr, TCR_KASAN_HW_FLAGS

1:

#endif

	msr	mair_el1, x5

	/*

	 * Set/prepare TCR and TTBR. TCR_EL1.T1SZ gets further

	 * adjusted if the kernel is compiled with 52bit VA support.
@@ -492,10 +492,13 @@ SYM_FUNC_START(__cpu_setup) 
	orr	x10, x10, #TCR_HA		// hardware Access flag update

1:

#endif	/* CONFIG_ARM64_HW_AFDBM */

	msr	mair_el1, mair

	msr	tcr_el1, x10

	/*

	 * Prepare SCTLR

	 */

	mov_q	x0, INIT_SCTLR_EL1_MMU_ON

	ret					// return to head.S



	.unreq	mair

SYM_FUNC_END(__cpu_setup)