clk: remove tango4 driver

* Sigma Designs Tango4 Clock Generator

The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used

for RAM and various peripheral devices). The clock binding described here

is applicable to all Tango4 SoCs.

Required Properties:

- compatible: should be "sigma,tango4-clkgen".

- reg: physical base address of the device and length of memory mapped region.

- clocks: phandle of the input clock (crystal oscillator).

- clock-output-names: should be "cpuclk" and "sysclk".

- #clock-cells: should be set to 1.

Example:

	clkgen: clkgen@10000 {

		compatible = "sigma,tango4-clkgen";

		reg = <0x10000 0x40>;

		clocks = <&xtal>;

		clock-output-names = "cpuclk", "sysclk";

		#clock-cells = <1>;

	};

obj-$(CONFIG_COMMON_CLK_STM32F)		+= clk-stm32f4.o

obj-$(CONFIG_COMMON_CLK_STM32H7)	+= clk-stm32h7.o

obj-$(CONFIG_COMMON_CLK_STM32MP157)	+= clk-stm32mp1.o

obj-$(CONFIG_ARCH_TANGO)		+= clk-tango4.o

obj-$(CONFIG_CLK_TWL6040)		+= clk-twl6040.o

obj-$(CONFIG_ARCH_U300)			+= clk-u300.o

obj-$(CONFIG_ARCH_VT8500)		+= clk-vt8500.o

// SPDX-License-Identifier: GPL-2.0

#include <linux/kernel.h>

#include <linux/clk-provider.h>

#include <linux/of_address.h>

#include <linux/init.h>

#include <linux/io.h>

#define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */

static struct clk *clks[CLK_COUNT];

static struct clk_onecell_data clk_data = { clks, CLK_COUNT };

#define SYSCLK_DIV	0x20

#define CPUCLK_DIV	0x24

#define DIV_BYPASS	BIT(23)

/*** CLKGEN_PLL ***/

#define extract_pll_n(val)	((val >>  0) & ((1u << 7) - 1))

#define extract_pll_k(val)	((val >> 13) & ((1u << 3) - 1))

#define extract_pll_m(val)	((val >> 16) & ((1u << 3) - 1))

#define extract_pll_isel(val)	((val >> 24) & ((1u << 3) - 1))

static void __init make_pll(int idx, const char *parent, void __iomem *base)

{

	char name[8];

	u32 val, mul, div;

	sprintf(name, "pll%d", idx);

	val = readl(base + idx * 8);

	mul =  extract_pll_n(val) + 1;

	div = (extract_pll_m(val) + 1) << extract_pll_k(val);

	clk_register_fixed_factor(NULL, name, parent, 0, mul, div);

	if (extract_pll_isel(val) != 1)

		panic("%s: input not set to XTAL_IN\n", name);

}

static void __init make_cd(int idx, void __iomem *base)

{

	char name[8];

	u32 val, mul, div;

	sprintf(name, "cd%d", idx);

	val = readl(base + idx * 8);

	mul =  1 << 27;

	div = (2 << 27) + val;

	clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div);

	if (val > 0xf0000000)

		panic("%s: unsupported divider %x\n", name, val);

}

static void __init tango4_clkgen_setup(struct device_node *np)

{

	struct clk **pp = clk_data.clks;

	void __iomem *base = of_iomap(np, 0);

	const char *parent = of_clk_get_parent_name(np, 0);

	if (!base)

		panic("%pOFn: invalid address\n", np);

	if (readl(base + CPUCLK_DIV) & DIV_BYPASS)

		panic("%pOFn: unsupported cpuclk setup\n", np);

	if (readl(base + SYSCLK_DIV) & DIV_BYPASS)

		panic("%pOFn: unsupported sysclk setup\n", np);

	writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */

	make_pll(0, parent, base);

	make_pll(1, parent, base);

	make_pll(2, parent, base);

	make_cd(2, base + 0x80);

	make_cd(6, base + 0x80);

	pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,

			base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);

	pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4);

	pp[2] = clk_register_fixed_factor(NULL,  "usb_clk", "cd2", 0, 1, 2);

	pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);

	if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3]))

		panic("%pOFn: clk registration failed\n", np);

	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))

		panic("%pOFn: clk provider registration failed\n", np);

}

CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);