Unverified Commit 771d6539 authored by Dave Stevenson's avatar Dave Stevenson Committed by Maxime Ripard
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drm/vc4: hdmi: Correct interlaced timings again 



The back porch timings were correct, only the sync offset was wrong.
Correct timing is now reported for 1080i and 576i, but the h offset is
incorrect for 480i for non-obvious reasons.

Fixes: fb10dc45 ("drm/vc4: hdmi: Correct HDMI timing registers for interlaced modes")
Signed-off-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20221207-rpi-hvs-crtc-misc-v1-14-1f8e0770798b@cerno.tech


Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent 273c4176

drivers/gpu/drm/vc4/vc4_hdmi.c

+3 −2
Original line number Diff line number Diff line
@@ -1307,11 +1307,12 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 
		     VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));

	u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),

				   VC5_HDMI_VERTB_VSPO) |

		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,

		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +

				   interlaced,

				   VC4_HDMI_VERTB_VBP));

	u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |

			  VC4_SET_FIELD(mode->crtc_vtotal -

					mode->crtc_vsync_end - interlaced,

					mode->crtc_vsync_end,

					VC4_HDMI_VERTB_VBP));

	unsigned long flags;

	unsigned char gcp;