Commit 76ebb289 authored by Zhiqi Song's avatar Zhiqi Song
Browse files

crypto: hisilicon/hpre - save capability registers in probe process 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7BANJ


CVE: NA

----------------------------------------------------------------------

Pre-store the valid value of hpre alg support related capability
register to a global array in hpre_qm_init(), which will be called
by hpre_probe(). It can reduce the number of capability register
queries and avoid obtaining incorrect values in abnormal scenarios,
such as reset failed and the memory space disabled.

Signed-off-by: default avatarZhiqi Song <songzhiqi1@huawei.com>
Signed-off-by: default avatarJiangShui Yang <yangjiangshui@h-partners.com>
parent b9b5cb5e

drivers/crypto/hisilicon/hpre/hpre_main.c

+26 −2
Original line number Diff line number Diff line
@@ -225,6 +225,16 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = { 
	{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}

};



enum hpre_cap_reg_record_idx {

	HPRE_DRV_ALG_BITMAP_CAP_IDX,

	HPRE_DEV_ALG_BITMAP_CAP_IDX,

};



static struct hisi_qm_cap_record hpre_cap_reg_record[] = {

	{HPRE_DRV_ALG_BITMAP_CAP,	0x27},

	{HPRE_DEV_ALG_BITMAP_CAP,	0x7F},

};



static const struct hpre_hw_error hpre_hw_errors[] = {

	{

		.int_msk = BIT(0),
@@ -344,7 +354,7 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) 
{

	u32 cap_val;



	cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver);

	cap_val = hpre_cap_reg_record[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val;

	if (alg & cap_val)

		return true;
@@ -1099,6 +1109,17 @@ static void hpre_debugfs_exit(struct hisi_qm *qm) 
	debugfs_remove_recursive(qm->debug.debug_root);

}



static void hpre_pre_store_cap_reg(struct hisi_qm *qm)

{

	int i, size;



	size = ARRAY_SIZE(hpre_cap_reg_record);

	for (i = 0; i < size; i++) {

		hpre_cap_reg_record[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info,

						 hpre_cap_reg_record[i].type, qm->cap_ver);

	}

}



static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)

{

	u64 alg_msk;
@@ -1132,7 +1153,10 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 
		return ret;

	}



	alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver);

	/* Fetch and save the value of capability registers */

	hpre_pre_store_cap_reg(qm);



	alg_msk = hpre_cap_reg_record[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val;

	ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));

	if (ret) {

		pci_err(pdev, "Failed to set hpre algs!\n");