Commit 76e6c73f authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/pmem: Update ppc64 to use the new barrier instruction. 



pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200701072235.223558-6-aneesh.kumar@linux.ibm.com
parent 3e79f082

arch/powerpc/include/asm/barrier.h

+13 −0
Original line number Diff line number Diff line
@@ -7,6 +7,10 @@ 


#include <asm/asm-const.h>



#ifndef __ASSEMBLY__

#include <asm/ppc-opcode.h>

#endif



/*

 * Memory barrier.

 * The sync instruction guarantees that all memory accesses initiated
@@ -97,6 +101,15 @@ do { \ 
#define barrier_nospec()

#endif /* CONFIG_PPC_BARRIER_NOSPEC */



/*

 * pmem_wmb() ensures that all stores for which the modification

 * are written to persistent storage by preceding dcbfps/dcbstps

 * instructions have updated persistent storage before any data

 * access or data transfer caused by subsequent instructions is

 * initiated.

 */

#define pmem_wmb() __asm__ __volatile__(PPC_PHWSYNC ::: "memory")



#include <asm-generic/barrier.h>



#endif /* _ASM_POWERPC_BARRIER_H */