Commit 76d136b5 authored by Brian Norris's avatar Brian Norris Committed by Chanwoo Choi
Browse files

dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties 



These DRAM configuration properties are all handled in ARM Trusted
Firmware (and have been since the early days of this SoC), and there are
no in-tree users of the DMC binding yet. It's better to just defer to
firmware instead of maintaining this large list of properties.

There's also some confusion about units: many of these are specified in
MHz, but the downstream users and driver code are treating them as Hz, I
believe. Rather than straighten all that out, I just drop them.

Signed-off-by: default avatarBrian Norris <briannorris@chromium.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
parent 2142c27e

Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml

+21 −21
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ properties: 
      finishes, a DCF interrupt is triggered.



  rockchip,ddr3_speed_bin:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
@@ -91,6 +92,7 @@ properties: 
      if bus is idle for standby_idle * DFI clock cycles.



  rockchip,dram_dll_dis_freq:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
@@ -98,6 +100,7 @@ properties: 
      Note: if DLL was bypassed, the odt will also stop working.



  rockchip,phy_dll_dis_freq:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
@@ -105,6 +108,7 @@ properties: 
      Note: PHY DLL and PHY ODT are independent.



  rockchip,auto_pd_dis_freq:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Defines the auto PD disable frequency in MHz.
@@ -118,6 +122,7 @@ properties: 
      disabled.



  rockchip,ddr3_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the DRAM side drive
@@ -125,6 +130,7 @@ properties: 
    default: 40



  rockchip,ddr3_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the DRAM side ODT
@@ -132,6 +138,7 @@ properties: 
    default: 120



  rockchip,phy_ddr3_ca_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the phy side CA line
@@ -139,6 +146,7 @@ properties: 
    default: 40



  rockchip,phy_ddr3_dq_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the PHY side DQ line
@@ -146,6 +154,7 @@ properties: 
    default: 40



  rockchip,phy_ddr3_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the PHY side ODT
@@ -161,6 +170,7 @@ properties: 
      disabled.



  rockchip,lpddr3_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
@@ -168,6 +178,7 @@ properties: 
    default: 34



  rockchip,lpddr3_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
@@ -175,6 +186,7 @@ properties: 
    default: 240



  rockchip,phy_lpddr3_ca_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
@@ -182,6 +194,7 @@ properties: 
    default: 40



  rockchip,phy_lpddr3_dq_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
@@ -189,6 +202,7 @@ properties: 
    default: 40



  rockchip,phy_lpddr3_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When dram type is LPDDR3, this parameter define the phy side odt
@@ -203,6 +217,7 @@ properties: 
      disabled.



  rockchip,lpddr4_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
@@ -210,6 +225,7 @@ properties: 
    default: 60



  rockchip,lpddr4_dq_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
@@ -217,6 +233,7 @@ properties: 
    default: 40



  rockchip,lpddr4_ca_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
@@ -224,6 +241,7 @@ properties: 
    default: 40



  rockchip,phy_lpddr4_ca_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
@@ -231,6 +249,7 @@ properties: 
    default: 40



  rockchip,phy_lpddr4_ck_cs_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the PHY side clock
@@ -238,6 +257,7 @@ properties: 
    default: 80



  rockchip,phy_lpddr4_dq_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
@@ -245,6 +265,7 @@ properties: 
    default: 80



  rockchip,phy_lpddr4_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
@@ -274,33 +295,12 @@ examples: 
      clock-names = "dmc_clk";

      operating-points-v2 = <&dmc_opp_table>;

      center-supply = <&ppvar_centerlogic>;

      rockchip,ddr3_speed_bin = <21>;

      rockchip,pd_idle = <0x40>;

      rockchip,sr_idle = <0x2>;

      rockchip,sr_mc_gate_idle = <0x3>;

      rockchip,srpd_lite_idle = <0x4>;

      rockchip,standby_idle = <0x2000>;

      rockchip,dram_dll_dis_freq = <300>;

      rockchip,phy_dll_dis_freq = <125>;

      rockchip,auto_pd_dis_freq = <666>;

      rockchip,ddr3_odt_dis_freq = <333>;

      rockchip,ddr3_drv = <40>;

      rockchip,ddr3_odt = <120>;

      rockchip,phy_ddr3_ca_drv = <40>;

      rockchip,phy_ddr3_dq_drv = <40>;

      rockchip,phy_ddr3_odt = <240>;

      rockchip,lpddr3_odt_dis_freq = <333>;

      rockchip,lpddr3_drv = <34>;

      rockchip,lpddr3_odt = <240>;

      rockchip,phy_lpddr3_ca_drv = <40>;

      rockchip,phy_lpddr3_dq_drv = <40>;

      rockchip,phy_lpddr3_odt = <240>;

      rockchip,lpddr4_odt_dis_freq = <333>;

      rockchip,lpddr4_drv = <60>;

      rockchip,lpddr4_dq_odt = <40>;

      rockchip,lpddr4_ca_odt = <40>;

      rockchip,phy_lpddr4_ca_drv = <40>;

      rockchip,phy_lpddr4_ck_cs_drv = <80>;

      rockchip,phy_lpddr4_dq_drv = <80>;

      rockchip,phy_lpddr4_odt = <60>;

    };