Commit 76873bb5 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

ARM: omap1: remove unused omapxxxx.h headers 



The only bit that is still in use is the OMAP_IH2_*_*
macros, so move them into the existing hardware.h file.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 9a99b142

arch/arm/mach-omap1/devices.c

+0 −1
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@ 
#include "tc.h"

#include "mux.h"



#include "omap7xx.h"

#include "hardware.h"

#include "common.h"

#include "clock.h"

arch/arm/mach-omap1/hardware.h

+44 −4
Original line number Diff line number Diff line
@@ -114,6 +114,10 @@ static inline u32 omap_cs3_phys(void) 


#define OMAP_IH1_BASE		0xfffecb00

#define OMAP_IH2_BASE		0xfffe0000

#define OMAP_IH2_0_BASE		(0xfffe0000)

#define OMAP_IH2_1_BASE		(0xfffe0100)

#define OMAP_IH2_2_BASE		(0xfffe0200)

#define OMAP_IH2_3_BASE		(0xfffe0300)



#define OMAP_IH1_ITR		(OMAP_IH1_BASE + 0x00)

#define OMAP_IH1_MIR		(OMAP_IH1_BASE + 0x04)
@@ -131,6 +135,38 @@ static inline u32 omap_cs3_phys(void) 
#define OMAP_IH2_ILR0		(OMAP_IH2_BASE + 0x1c)

#define OMAP_IH2_ISR		(OMAP_IH2_BASE + 0x9c)



#define OMAP_IH2_0_ITR		(OMAP_IH2_0_BASE + 0x00)

#define OMAP_IH2_0_MIR		(OMAP_IH2_0_BASE + 0x04)

#define OMAP_IH2_0_SIR_IRQ	(OMAP_IH2_0_BASE + 0x10)

#define OMAP_IH2_0_SIR_FIQ	(OMAP_IH2_0_BASE + 0x14)

#define OMAP_IH2_0_CONTROL	(OMAP_IH2_0_BASE + 0x18)

#define OMAP_IH2_0_ILR0		(OMAP_IH2_0_BASE + 0x1c)

#define OMAP_IH2_0_ISR		(OMAP_IH2_0_BASE + 0x9c)



#define OMAP_IH2_1_ITR		(OMAP_IH2_1_BASE + 0x00)

#define OMAP_IH2_1_MIR		(OMAP_IH2_1_BASE + 0x04)

#define OMAP_IH2_1_SIR_IRQ	(OMAP_IH2_1_BASE + 0x10)

#define OMAP_IH2_1_SIR_FIQ	(OMAP_IH2_1_BASE + 0x14)

#define OMAP_IH2_1_CONTROL	(OMAP_IH2_1_BASE + 0x18)

#define OMAP_IH2_1_ILR1		(OMAP_IH2_1_BASE + 0x1c)

#define OMAP_IH2_1_ISR		(OMAP_IH2_1_BASE + 0x9c)



#define OMAP_IH2_2_ITR		(OMAP_IH2_2_BASE + 0x00)

#define OMAP_IH2_2_MIR		(OMAP_IH2_2_BASE + 0x04)

#define OMAP_IH2_2_SIR_IRQ	(OMAP_IH2_2_BASE + 0x10)

#define OMAP_IH2_2_SIR_FIQ	(OMAP_IH2_2_BASE + 0x14)

#define OMAP_IH2_2_CONTROL	(OMAP_IH2_2_BASE + 0x18)

#define OMAP_IH2_2_ILR2		(OMAP_IH2_2_BASE + 0x1c)

#define OMAP_IH2_2_ISR		(OMAP_IH2_2_BASE + 0x9c)



#define OMAP_IH2_3_ITR		(OMAP_IH2_3_BASE + 0x00)

#define OMAP_IH2_3_MIR		(OMAP_IH2_3_BASE + 0x04)

#define OMAP_IH2_3_SIR_IRQ	(OMAP_IH2_3_BASE + 0x10)

#define OMAP_IH2_3_SIR_FIQ	(OMAP_IH2_3_BASE + 0x14)

#define OMAP_IH2_3_CONTROL	(OMAP_IH2_3_BASE + 0x18)

#define OMAP_IH2_3_ILR3		(OMAP_IH2_3_BASE + 0x1c)

#define OMAP_IH2_3_ISR		(OMAP_IH2_3_BASE + 0x9c)



#define IRQ_ITR_REG_OFFSET	0x00

#define IRQ_MIR_REG_OFFSET	0x04

#define IRQ_SIR_IRQ_REG_OFFSET	0x10
@@ -184,12 +220,16 @@ static inline u32 omap_cs3_phys(void) 


/*

 * ---------------------------------------------------------------------------

 * Processor specific defines

 * DSP

 * ---------------------------------------------------------------------------

 */



#include "omap7xx.h"

#include "omap1510.h"

#include "omap16xx.h"

#define OMAP1_DSP_BASE		0xE0000000

#define OMAP1_DSP_SIZE		0x28000

#define OMAP1_DSP_START		0xE0000000



#define OMAP1_DSPREG_BASE	0xE1000000

#define OMAP1_DSPREG_SIZE	SZ_128K

#define OMAP1_DSPREG_START	0xE1000000



#endif	/* __ASM_ARCH_OMAP_HARDWARE_H */

arch/arm/mach-omap1/omap1510.h

deleted100644 → 0
+0 −162
Original line number Diff line number Diff line 
/*

 * Hardware definitions for TI OMAP1510 processor.

 *

 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License as published by the

 * Free Software Foundation; either version 2 of the License, or (at your

 * option) any later version.

 *

 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED

 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN

 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,

 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT

 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF

 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON

 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 *

 * You should have received a copy of the  GNU General Public License along

 * with this program; if not, write  to the Free Software Foundation, Inc.,

 * 675 Mass Ave, Cambridge, MA 02139, USA.

 */



#ifndef __ASM_ARCH_OMAP15XX_H

#define __ASM_ARCH_OMAP15XX_H



/*

 * ----------------------------------------------------------------------------

 * Base addresses

 * ----------------------------------------------------------------------------

 */



/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */



#define OMAP1510_DSP_BASE	0xE0000000

#define OMAP1510_DSP_SIZE	0x28000

#define OMAP1510_DSP_START	0xE0000000



#define OMAP1510_DSPREG_BASE	0xE1000000

#define OMAP1510_DSPREG_SIZE	SZ_128K

#define OMAP1510_DSPREG_START	0xE1000000



#define OMAP1510_DSP_MMU_BASE	(0xfffed200)



/*

 * ---------------------------------------------------------------------------

 *  OMAP-1510 FPGA

 * ---------------------------------------------------------------------------

 */

#define OMAP1510_FPGA_BASE		0xE8000000		/* VA */

#define OMAP1510_FPGA_SIZE		SZ_4K

#define OMAP1510_FPGA_START		0x08000000		/* PA */



/* Revision */

#define OMAP1510_FPGA_REV_LOW			IOMEM(OMAP1510_FPGA_BASE + 0x0)

#define OMAP1510_FPGA_REV_HIGH			IOMEM(OMAP1510_FPGA_BASE + 0x1)

#define OMAP1510_FPGA_LCD_PANEL_CONTROL		IOMEM(OMAP1510_FPGA_BASE + 0x2)

#define OMAP1510_FPGA_LED_DIGIT			IOMEM(OMAP1510_FPGA_BASE + 0x3)

#define INNOVATOR_FPGA_HID_SPI			IOMEM(OMAP1510_FPGA_BASE + 0x4)

#define OMAP1510_FPGA_POWER			IOMEM(OMAP1510_FPGA_BASE + 0x5)



/* Interrupt status */

#define OMAP1510_FPGA_ISR_LO			IOMEM(OMAP1510_FPGA_BASE + 0x6)

#define OMAP1510_FPGA_ISR_HI			IOMEM(OMAP1510_FPGA_BASE + 0x7)



/* Interrupt mask */

#define OMAP1510_FPGA_IMR_LO			IOMEM(OMAP1510_FPGA_BASE + 0x8)

#define OMAP1510_FPGA_IMR_HI			IOMEM(OMAP1510_FPGA_BASE + 0x9)



/* Reset registers */

#define OMAP1510_FPGA_HOST_RESET		IOMEM(OMAP1510_FPGA_BASE + 0xa)

#define OMAP1510_FPGA_RST			IOMEM(OMAP1510_FPGA_BASE + 0xb)



#define OMAP1510_FPGA_AUDIO			IOMEM(OMAP1510_FPGA_BASE + 0xc)

#define OMAP1510_FPGA_DIP			IOMEM(OMAP1510_FPGA_BASE + 0xe)

#define OMAP1510_FPGA_FPGA_IO			IOMEM(OMAP1510_FPGA_BASE + 0xf)

#define OMAP1510_FPGA_UART1			IOMEM(OMAP1510_FPGA_BASE + 0x14)

#define OMAP1510_FPGA_UART2			IOMEM(OMAP1510_FPGA_BASE + 0x15)

#define OMAP1510_FPGA_OMAP1510_STATUS		IOMEM(OMAP1510_FPGA_BASE + 0x16)

#define OMAP1510_FPGA_BOARD_REV			IOMEM(OMAP1510_FPGA_BASE + 0x18)

#define INNOVATOR_FPGA_CAM_USB_CONTROL		IOMEM(OMAP1510_FPGA_BASE + 0x20c)

#define OMAP1510P1_PPT_DATA			IOMEM(OMAP1510_FPGA_BASE + 0x100)

#define OMAP1510P1_PPT_STATUS			IOMEM(OMAP1510_FPGA_BASE + 0x101)

#define OMAP1510P1_PPT_CONTROL			IOMEM(OMAP1510_FPGA_BASE + 0x102)



#define OMAP1510_FPGA_TOUCHSCREEN		IOMEM(OMAP1510_FPGA_BASE + 0x204)



#define INNOVATOR_FPGA_INFO			IOMEM(OMAP1510_FPGA_BASE + 0x205)

#define INNOVATOR_FPGA_LCD_BRIGHT_LO		IOMEM(OMAP1510_FPGA_BASE + 0x206)

#define INNOVATOR_FPGA_LCD_BRIGHT_HI		IOMEM(OMAP1510_FPGA_BASE + 0x207)

#define INNOVATOR_FPGA_LED_GRN_LO		IOMEM(OMAP1510_FPGA_BASE + 0x208)

#define INNOVATOR_FPGA_LED_GRN_HI		IOMEM(OMAP1510_FPGA_BASE + 0x209)

#define INNOVATOR_FPGA_LED_RED_LO		IOMEM(OMAP1510_FPGA_BASE + 0x20a)

#define INNOVATOR_FPGA_LED_RED_HI		IOMEM(OMAP1510_FPGA_BASE + 0x20b)

#define INNOVATOR_FPGA_EXP_CONTROL		IOMEM(OMAP1510_FPGA_BASE + 0x20d)

#define INNOVATOR_FPGA_ISR2			IOMEM(OMAP1510_FPGA_BASE + 0x20e)

#define INNOVATOR_FPGA_IMR2			IOMEM(OMAP1510_FPGA_BASE + 0x210)



#define OMAP1510_FPGA_ETHR_START		(OMAP1510_FPGA_START + 0x300)



/*

 * Power up Giga UART driver, turn on HID clock.

 * Turn off BT power, since we're not using it and it

 * draws power.

 */

#define OMAP1510_FPGA_RESET_VALUE		0x42



#define OMAP1510_FPGA_PCR_IF_PD0		(1 << 7)

#define OMAP1510_FPGA_PCR_COM2_EN		(1 << 6)

#define OMAP1510_FPGA_PCR_COM1_EN		(1 << 5)

#define OMAP1510_FPGA_PCR_EXP_PD0		(1 << 4)

#define OMAP1510_FPGA_PCR_EXP_PD1		(1 << 3)

#define OMAP1510_FPGA_PCR_48MHZ_CLK		(1 << 2)

#define OMAP1510_FPGA_PCR_4MHZ_CLK		(1 << 1)

#define OMAP1510_FPGA_PCR_RSRVD_BIT0		(1 << 0)



/*

 * Innovator/OMAP1510 FPGA HID register bit definitions

 */

#define OMAP1510_FPGA_HID_SCLK	(1<<0)	/* output */

#define OMAP1510_FPGA_HID_MOSI	(1<<1)	/* output */

#define OMAP1510_FPGA_HID_nSS	(1<<2)	/* output 0/1 chip idle/select */

#define OMAP1510_FPGA_HID_nHSUS	(1<<3)	/* output 0/1 host active/suspended */

#define OMAP1510_FPGA_HID_MISO	(1<<4)	/* input */

#define OMAP1510_FPGA_HID_ATN	(1<<5)	/* input  0/1 chip idle/ATN */

#define OMAP1510_FPGA_HID_rsrvd	(1<<6)

#define OMAP1510_FPGA_HID_RESETn (1<<7)	/* output - 0/1 USAR reset/run */



/* The FPGA IRQ is cascaded through GPIO_13 */

#define OMAP1510_INT_FPGA		(IH_GPIO_BASE + 13)



/* IRQ Numbers for interrupts muxed through the FPGA */

#define OMAP1510_INT_FPGA_ATN		(OMAP_FPGA_IRQ_BASE + 0)

#define OMAP1510_INT_FPGA_ACK		(OMAP_FPGA_IRQ_BASE + 1)

#define OMAP1510_INT_FPGA2		(OMAP_FPGA_IRQ_BASE + 2)

#define OMAP1510_INT_FPGA3		(OMAP_FPGA_IRQ_BASE + 3)

#define OMAP1510_INT_FPGA4		(OMAP_FPGA_IRQ_BASE + 4)

#define OMAP1510_INT_FPGA5		(OMAP_FPGA_IRQ_BASE + 5)

#define OMAP1510_INT_FPGA6		(OMAP_FPGA_IRQ_BASE + 6)

#define OMAP1510_INT_FPGA7		(OMAP_FPGA_IRQ_BASE + 7)

#define OMAP1510_INT_FPGA8		(OMAP_FPGA_IRQ_BASE + 8)

#define OMAP1510_INT_FPGA9		(OMAP_FPGA_IRQ_BASE + 9)

#define OMAP1510_INT_FPGA10		(OMAP_FPGA_IRQ_BASE + 10)

#define OMAP1510_INT_FPGA11		(OMAP_FPGA_IRQ_BASE + 11)

#define OMAP1510_INT_FPGA12		(OMAP_FPGA_IRQ_BASE + 12)

#define OMAP1510_INT_ETHER		(OMAP_FPGA_IRQ_BASE + 13)

#define OMAP1510_INT_FPGAUART1		(OMAP_FPGA_IRQ_BASE + 14)

#define OMAP1510_INT_FPGAUART2		(OMAP_FPGA_IRQ_BASE + 15)

#define OMAP1510_INT_FPGA_TS		(OMAP_FPGA_IRQ_BASE + 16)

#define OMAP1510_INT_FPGA17		(OMAP_FPGA_IRQ_BASE + 17)

#define OMAP1510_INT_FPGA_CAM		(OMAP_FPGA_IRQ_BASE + 18)

#define OMAP1510_INT_FPGA_RTC_A		(OMAP_FPGA_IRQ_BASE + 19)

#define OMAP1510_INT_FPGA_RTC_B		(OMAP_FPGA_IRQ_BASE + 20)

#define OMAP1510_INT_FPGA_CD		(OMAP_FPGA_IRQ_BASE + 21)

#define OMAP1510_INT_FPGA22		(OMAP_FPGA_IRQ_BASE + 22)

#define OMAP1510_INT_FPGA23		(OMAP_FPGA_IRQ_BASE + 23)



#endif /*  __ASM_ARCH_OMAP15XX_H */

arch/arm/mach-omap1/omap16xx.h

deleted100644 → 0
+0 −201
Original line number Diff line number Diff line 
/*

 * Hardware definitions for TI OMAP1610/5912/1710 processors.

 *

 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License as published by the

 * Free Software Foundation; either version 2 of the License, or (at your

 * option) any later version.

 *

 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED

 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN

 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,

 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT

 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF

 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON

 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 *

 * You should have received a copy of the  GNU General Public License along

 * with this program; if not, write  to the Free Software Foundation, Inc.,

 * 675 Mass Ave, Cambridge, MA 02139, USA.

 */



#ifndef __ASM_ARCH_OMAP16XX_H

#define __ASM_ARCH_OMAP16XX_H



/*

 * ----------------------------------------------------------------------------

 * Base addresses

 * ----------------------------------------------------------------------------

 */



/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */



#define OMAP16XX_DSP_BASE	0xE0000000

#define OMAP16XX_DSP_SIZE	0x28000

#define OMAP16XX_DSP_START	0xE0000000



#define OMAP16XX_DSPREG_BASE	0xE1000000

#define OMAP16XX_DSPREG_SIZE	SZ_128K

#define OMAP16XX_DSPREG_START	0xE1000000



#define OMAP16XX_SEC_BASE	0xFFFE4000

#define OMAP16XX_SEC_DES	(OMAP16XX_SEC_BASE + 0x0000)

#define OMAP16XX_SEC_SHA1MD5	(OMAP16XX_SEC_BASE + 0x0800)

#define OMAP16XX_SEC_RNG	(OMAP16XX_SEC_BASE + 0x1000)



/*

 * ---------------------------------------------------------------------------

 * Interrupts

 * ---------------------------------------------------------------------------

 */

#define OMAP_IH2_0_BASE		(0xfffe0000)

#define OMAP_IH2_1_BASE		(0xfffe0100)

#define OMAP_IH2_2_BASE		(0xfffe0200)

#define OMAP_IH2_3_BASE		(0xfffe0300)



#define OMAP_IH2_0_ITR		(OMAP_IH2_0_BASE + 0x00)

#define OMAP_IH2_0_MIR		(OMAP_IH2_0_BASE + 0x04)

#define OMAP_IH2_0_SIR_IRQ	(OMAP_IH2_0_BASE + 0x10)

#define OMAP_IH2_0_SIR_FIQ	(OMAP_IH2_0_BASE + 0x14)

#define OMAP_IH2_0_CONTROL	(OMAP_IH2_0_BASE + 0x18)

#define OMAP_IH2_0_ILR0		(OMAP_IH2_0_BASE + 0x1c)

#define OMAP_IH2_0_ISR		(OMAP_IH2_0_BASE + 0x9c)



#define OMAP_IH2_1_ITR		(OMAP_IH2_1_BASE + 0x00)

#define OMAP_IH2_1_MIR		(OMAP_IH2_1_BASE + 0x04)

#define OMAP_IH2_1_SIR_IRQ	(OMAP_IH2_1_BASE + 0x10)

#define OMAP_IH2_1_SIR_FIQ	(OMAP_IH2_1_BASE + 0x14)

#define OMAP_IH2_1_CONTROL	(OMAP_IH2_1_BASE + 0x18)

#define OMAP_IH2_1_ILR1		(OMAP_IH2_1_BASE + 0x1c)

#define OMAP_IH2_1_ISR		(OMAP_IH2_1_BASE + 0x9c)



#define OMAP_IH2_2_ITR		(OMAP_IH2_2_BASE + 0x00)

#define OMAP_IH2_2_MIR		(OMAP_IH2_2_BASE + 0x04)

#define OMAP_IH2_2_SIR_IRQ	(OMAP_IH2_2_BASE + 0x10)

#define OMAP_IH2_2_SIR_FIQ	(OMAP_IH2_2_BASE + 0x14)

#define OMAP_IH2_2_CONTROL	(OMAP_IH2_2_BASE + 0x18)

#define OMAP_IH2_2_ILR2		(OMAP_IH2_2_BASE + 0x1c)

#define OMAP_IH2_2_ISR		(OMAP_IH2_2_BASE + 0x9c)



#define OMAP_IH2_3_ITR		(OMAP_IH2_3_BASE + 0x00)

#define OMAP_IH2_3_MIR		(OMAP_IH2_3_BASE + 0x04)

#define OMAP_IH2_3_SIR_IRQ	(OMAP_IH2_3_BASE + 0x10)

#define OMAP_IH2_3_SIR_FIQ	(OMAP_IH2_3_BASE + 0x14)

#define OMAP_IH2_3_CONTROL	(OMAP_IH2_3_BASE + 0x18)

#define OMAP_IH2_3_ILR3		(OMAP_IH2_3_BASE + 0x1c)

#define OMAP_IH2_3_ISR		(OMAP_IH2_3_BASE + 0x9c)



/*

 * ----------------------------------------------------------------------------

 * Clocks

 * ----------------------------------------------------------------------------

 */

#define OMAP16XX_ARM_IDLECT3	(CLKGEN_REG_BASE + 0x24)



/*

 * ----------------------------------------------------------------------------

 * Pin configuration registers

 * ----------------------------------------------------------------------------

 */

#define OMAP16XX_CONF_VOLTAGE_VDDSHV6	(1 << 8)

#define OMAP16XX_CONF_VOLTAGE_VDDSHV7	(1 << 9)

#define OMAP16XX_CONF_VOLTAGE_VDDSHV8	(1 << 10)

#define OMAP16XX_CONF_VOLTAGE_VDDSHV9	(1 << 11)

#define OMAP16XX_SUBLVDS_CONF_VALID	(1 << 13)



/*

 * ----------------------------------------------------------------------------

 * System control registers

 * ----------------------------------------------------------------------------

 */

#define OMAP1610_RESET_CONTROL  0xfffe1140



/*

 * ---------------------------------------------------------------------------

 * TIPB bus interface

 * ---------------------------------------------------------------------------

 */

#define TIPB_SWITCH_BASE		 (0xfffbc800)

#define OMAP16XX_MMCSD2_SSW_MPU_CONF	(TIPB_SWITCH_BASE + 0x160)



/* UART3 Registers Mapping through MPU bus */

#define UART3_RHR               (OMAP1_UART3_BASE + 0)

#define UART3_THR               (OMAP1_UART3_BASE + 0)

#define UART3_DLL               (OMAP1_UART3_BASE + 0)

#define UART3_IER               (OMAP1_UART3_BASE + 4)

#define UART3_DLH               (OMAP1_UART3_BASE + 4)

#define UART3_IIR               (OMAP1_UART3_BASE + 8)

#define UART3_FCR               (OMAP1_UART3_BASE + 8)

#define UART3_EFR               (OMAP1_UART3_BASE + 8)

#define UART3_LCR               (OMAP1_UART3_BASE + 0x0C)

#define UART3_MCR               (OMAP1_UART3_BASE + 0x10)

#define UART3_XON1_ADDR1        (OMAP1_UART3_BASE + 0x10)

#define UART3_XON2_ADDR2        (OMAP1_UART3_BASE + 0x14)

#define UART3_LSR               (OMAP1_UART3_BASE + 0x14)

#define UART3_TCR               (OMAP1_UART3_BASE + 0x18)

#define UART3_MSR               (OMAP1_UART3_BASE + 0x18)

#define UART3_XOFF1             (OMAP1_UART3_BASE + 0x18)

#define UART3_XOFF2             (OMAP1_UART3_BASE + 0x1C)

#define UART3_SPR               (OMAP1_UART3_BASE + 0x1C)

#define UART3_TLR               (OMAP1_UART3_BASE + 0x1C)

#define UART3_MDR1              (OMAP1_UART3_BASE + 0x20)

#define UART3_MDR2              (OMAP1_UART3_BASE + 0x24)

#define UART3_SFLSR             (OMAP1_UART3_BASE + 0x28)

#define UART3_TXFLL             (OMAP1_UART3_BASE + 0x28)

#define UART3_RESUME            (OMAP1_UART3_BASE + 0x2C)

#define UART3_TXFLH             (OMAP1_UART3_BASE + 0x2C)

#define UART3_SFREGL            (OMAP1_UART3_BASE + 0x30)

#define UART3_RXFLL             (OMAP1_UART3_BASE + 0x30)

#define UART3_SFREGH            (OMAP1_UART3_BASE + 0x34)

#define UART3_RXFLH             (OMAP1_UART3_BASE + 0x34)

#define UART3_BLR               (OMAP1_UART3_BASE + 0x38)

#define UART3_ACREG             (OMAP1_UART3_BASE + 0x3C)

#define UART3_DIV16             (OMAP1_UART3_BASE + 0x3C)

#define UART3_SCR               (OMAP1_UART3_BASE + 0x40)

#define UART3_SSR               (OMAP1_UART3_BASE + 0x44)

#define UART3_EBLR              (OMAP1_UART3_BASE + 0x48)

#define UART3_OSC_12M_SEL       (OMAP1_UART3_BASE + 0x4C)

#define UART3_MVR               (OMAP1_UART3_BASE + 0x50)



/*

 * ---------------------------------------------------------------------------

 * Watchdog timer

 * ---------------------------------------------------------------------------

 */



/* 32-bit Watchdog timer in OMAP 16XX */

#define OMAP_16XX_WATCHDOG_BASE        (0xfffeb000)

#define OMAP_16XX_WIDR         (OMAP_16XX_WATCHDOG_BASE + 0x00)

#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)

#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)

#define OMAP_16XX_WCLR         (OMAP_16XX_WATCHDOG_BASE + 0x24)

#define OMAP_16XX_WCRR         (OMAP_16XX_WATCHDOG_BASE + 0x28)

#define OMAP_16XX_WLDR         (OMAP_16XX_WATCHDOG_BASE + 0x2c)

#define OMAP_16XX_WTGR         (OMAP_16XX_WATCHDOG_BASE + 0x30)

#define OMAP_16XX_WWPS         (OMAP_16XX_WATCHDOG_BASE + 0x34)

#define OMAP_16XX_WSPR         (OMAP_16XX_WATCHDOG_BASE + 0x48)



#define WCLR_PRE_SHIFT         5

#define WCLR_PTV_SHIFT         2



#define WWPS_W_PEND_WSPR       (1 << 4)

#define WWPS_W_PEND_WTGR       (1 << 3)

#define WWPS_W_PEND_WLDR       (1 << 2)

#define WWPS_W_PEND_WCRR       (1 << 1)

#define WWPS_W_PEND_WCLR       (1 << 0)



#define WSPR_ENABLE_0          (0x0000bbbb)

#define WSPR_ENABLE_1          (0x00004444)

#define WSPR_DISABLE_0         (0x0000aaaa)

#define WSPR_DISABLE_1         (0x00005555)



#define OMAP16XX_DSP_MMU_BASE	(0xfffed200)

#define OMAP16XX_MAILBOX_BASE	(0xfffcf000)



#endif /*  __ASM_ARCH_OMAP16XX_H */

arch/arm/mach-omap1/omap7xx.h

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Original line number Diff line number Diff line 
/*

 * Hardware definitions for TI OMAP7XX processor.

 *

 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>

 * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>

 * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License as published by the

 * Free Software Foundation; either version 2 of the License, or (at your

 * option) any later version.

 *

 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED

 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN

 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,

 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT

 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF

 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON

 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 *

 * You should have received a copy of the  GNU General Public License along

 * with this program; if not, write  to the Free Software Foundation, Inc.,

 * 675 Mass Ave, Cambridge, MA 02139, USA.

 */



#ifndef __ASM_ARCH_OMAP7XX_H

#define __ASM_ARCH_OMAP7XX_H



/*

 * ----------------------------------------------------------------------------

 * Base addresses

 * ----------------------------------------------------------------------------

 */



/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */



#define OMAP7XX_DSP_BASE	0xE0000000

#define OMAP7XX_DSP_SIZE	0x50000

#define OMAP7XX_DSP_START	0xE0000000



#define OMAP7XX_DSPREG_BASE	0xE1000000

#define OMAP7XX_DSPREG_SIZE	SZ_128K

#define OMAP7XX_DSPREG_START	0xE1000000



#define OMAP7XX_SPI1_BASE	0xfffc0800

#define OMAP7XX_SPI2_BASE	0xfffc1000



/*

 * ----------------------------------------------------------------------------

 * OMAP7XX specific configuration registers

 * ----------------------------------------------------------------------------

 */

#define OMAP7XX_CONFIG_BASE	0xfffe1000

#define OMAP7XX_IO_CONF_0	0xfffe1070

#define OMAP7XX_IO_CONF_1	0xfffe1074

#define OMAP7XX_IO_CONF_2	0xfffe1078

#define OMAP7XX_IO_CONF_3	0xfffe107c

#define OMAP7XX_IO_CONF_4	0xfffe1080

#define OMAP7XX_IO_CONF_5	0xfffe1084

#define OMAP7XX_IO_CONF_6	0xfffe1088

#define OMAP7XX_IO_CONF_7	0xfffe108c

#define OMAP7XX_IO_CONF_8	0xfffe1090

#define OMAP7XX_IO_CONF_9	0xfffe1094

#define OMAP7XX_IO_CONF_10	0xfffe1098

#define OMAP7XX_IO_CONF_11	0xfffe109c

#define OMAP7XX_IO_CONF_12	0xfffe10a0

#define OMAP7XX_IO_CONF_13	0xfffe10a4



#define OMAP7XX_MODE_1		0xfffe1010

#define OMAP7XX_MODE_2		0xfffe1014



/* CSMI specials: in terms of base + offset */

#define OMAP7XX_MODE2_OFFSET	0x14



/*

 * ----------------------------------------------------------------------------

 * OMAP7XX traffic controller configuration registers

 * ----------------------------------------------------------------------------

 */

#define OMAP7XX_FLASH_CFG_0	0xfffecc10

#define OMAP7XX_FLASH_ACFG_0	0xfffecc50

#define OMAP7XX_FLASH_CFG_1	0xfffecc14

#define OMAP7XX_FLASH_ACFG_1	0xfffecc54



/*

 * ----------------------------------------------------------------------------

 * OMAP7XX DSP control registers

 * ----------------------------------------------------------------------------

 */

#define OMAP7XX_ICR_BASE	0xfffbb800

#define OMAP7XX_DSP_M_CTL	0xfffbb804

#define OMAP7XX_DSP_MMU_BASE	0xfffed200



/*

 * ----------------------------------------------------------------------------

 * OMAP7XX PCC_UPLD configuration registers

 * ----------------------------------------------------------------------------

 */

#define OMAP7XX_PCC_UPLD_CTRL_BASE	(0xfffe0900)

#define OMAP7XX_PCC_UPLD_CTRL		(OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)



#endif /*  __ASM_ARCH_OMAP7XX_H */