sw64: add CPU definition headers

/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_SW64_CORE_H

#define _ASM_SW64_CORE_H

#include <asm/csr.h>

#define II_II0			0

#define II_II1			1

#define II_SLEEP		2

#define II_WAKE			3

#define II_NMII			6

#define II_RESET		II_NMII

#if defined(CONFIG_SUBARCH_C3B)

#define DOMAIN_ID_BITS		2

#define DOMAIN_ID_SHIFT		5

#define THREAD_ID_BITS		1

#define THREAD_ID_SHIFT		31

#define CORE_ID_BITS		5

#define CORE_ID_SHIFT		0

static inline bool core_is_ht(void)

{

	return 0;

}

#elif defined(CONFIG_SUBARCH_C4)

#define DOMAIN_ID_BITS		2

#define DOMAIN_ID_SHIFT		12

#define THREAD_ID_BITS		1

#define THREAD_ID_SHIFT		8

#define CORE_ID_BITS		6

#define CORE_ID_SHIFT		0

static inline bool core_is_ht(void)

{

	return rdhtctl() == 0x3;

}

#endif

#define DOMAIN_ID_MASK		(GENMASK(DOMAIN_ID_BITS - 1, 0) << DOMAIN_ID_SHIFT)

#define THREAD_ID_MASK		(GENMASK(THREAD_ID_BITS - 1, 0) << THREAD_ID_SHIFT)

#define CORE_ID_MASK		(GENMASK(CORE_ID_BITS - 1, 0) << CORE_ID_SHIFT)

#define MAX_CORES_PER_CPU	(1 << CORE_ID_BITS)

/*

 * 0x00 ~ 0xff for hardware mm fault

 */

#define MMCSR__TNV		0x0

#define MMCSR__IACV		0x1

#define MMCSR__FOR		0x2

#define MMCSR__FOE		0x3

#define MMCSR__FOW		0x4

#define MMCSR__BAD_DVA		0x6

#define MMCSR__ACV1		0x7

#define MMCSR__ACV0		0xc

#define MMCSR__BAD_IVA		0xf

/* 0x100 ~ 0x1ff for match debug */

#define MMCSR__DA_MATCH		0x100

#define MMCSR__DV_MATCH		0x101

#define MMCSR__DAV_MATCH	0x102

#define MMCSR__IA_MATCH		0x103

#define MMCSR__IDA_MATCH	0x104

#define MMCSR__IV_MATCH		0x105

 /* entry.S */

extern void entArith(void);

extern void entIF(void);

extern void entInt(void);

extern void entMM(void);

extern void entSys(void);

extern void entUna(void);

/* head.S */

extern void __smp_callin(unsigned long args);

#endif /* _ASM_SW64_CORE_H */

/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_SW64_CPU_H

#define _ASM_SW64_CPU_H

#endif /* _ASM_SW64_CPU_H */

/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_SW64_CSR_H

#define _ASM_SW64_CSR_H

#include <asm/hmcall.h>

#define CSR_EXC_SUM		0xd

#define CSR_INT_EN		0x1a

#define CSR_INT_STAT		0x1b

#define CSR_PCIE_MSI0_INT	0x1d

#define CSR_PCIE_MSI1_INT	0x1e

#define CSR_PCIE_MSI2_INT	0x1f

#define CSR_PCIE_MSI3_INT	0x20

#define CSR_INT_VEC		0x2d

#define CSR_PCIE_MSI0_INTEN	0x35

#define CSR_PCIE_MSI1_INTEN	0x36

#define CSR_PCIE_MSI2_INTEN	0x37

#define CSR_PCIE_MSI3_INTEN	0x38

#define CSR_EXC_GPA		0x3b

#define CSR_EXC_PC		0xe

#define CSR_AS_INFO		0x3c

#define CSR_DS_STAT		0x48

#define CSR_SOFTCID		0xc9

#define CSR_DVA			0x54

#define CSR_PTBR_SYS		0x68

#define CSR_PTBR_USR		0x69

#define CSR_APTP		0x6a

#define CSR_CID			0xc4

#define CSR_WR_FREGS		0xc8

#define CSR_SHTCLOCK		0xca

#define CSR_SHTCLOCK_OFFSET	0xcb

#ifdef CONFIG_SUBARCH_C4

#define CSR_IA_VPNMATCH		0xa

#define CSR_UPCR		0x15

#define CSR_VPCR		0x16

#define CSR_IA_MATCH		0x17

#define CSR_IA_MASK		0x18

#define CSR_IV_MATCH		0x19

#define CSR_IA_UPNMATCH		0x3a

#define CSR_DC_CTLP		0x4e

#define CSR_DA_MATCH		0x51

#define CSR_DA_MASK		0x52

#define CSR_DA_MATCH_MODE	0x53

#define CSR_DV_MATCH		0x56

#define CSR_DV_MASK		0x57

#define CSR_IDA_MATCH		0xc5

#define CSR_IDA_MASK		0xc6

#define DA_MATCH_EN_S		4

#define DV_MATCH_EN_S		6

#define DAV_MATCH_EN_S		7

#define DPM_MATCH		8

#define DPM_MATCH_EN_S		10

#define IDA_MATCH_EN_S		53

#define IV_PM_EN_S		61

#define IV_MATCH_EN_S		62

#define IA_MATCH_EN_S		63

#endif

#ifdef CONFIG_HAVE_CSRRW

#define read_csr(x)					\

	({ unsigned long __val;				\

	 __asm__ __volatile__("csrr %0,%1" : "=r"(__val) : "i"(x));	\

	 __val; })

#define write_csr(x, y)					\

	({ __asm__ __volatile__("csrw %0,%1" ::"r"(x), "i"(y)); })

#define write_csr_imb(x, y)				\

	({ __asm__ __volatile__("csrw %0,%1; imemb" ::"r"(x), "i"(y)); })

#ifndef __ASSEMBLY__

#include <asm/barrier.h>

static inline void update_ptbr_sys(unsigned long ptbr)

{

	imemb();

	write_csr_imb(ptbr, CSR_PTBR_SYS);

}

#endif

#else

#define read_csr(x)			(0)

#define write_csr(x, y)			do { } while (0)

#define write_csr_imb(x, y)		do { } while (0)

#ifndef __ASSEMBLY__

static inline void update_ptbr_sys(unsigned long ptbr)

{

	wrptbr(ptbr);

}

#endif

#endif

#endif /* _ASM_SW64_CSR_H */

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */

#ifndef _UAPI_ASM_SW64_REGDEF_H

#define _UAPI_ASM_SW64_REGDEF_H

#define v0	$0	/* function return value */

#define t0	$1	/* temporary registers (caller-saved) */

#define t1	$2

#define t2	$3

#define t3	$4

#define t4	$5

#define t5	$6

#define t6	$7

#define t7	$8

#define s0	$9	/* saved-registers (callee-saved registers) */

#define s1	$10

#define s2	$11

#define s3	$12

#define s4	$13

#define s5	$14

#define s6	$15

#define fp	s6	/* frame-pointer (s6 in frame-less procedures) */

#define a0	$16	/* argument registers (caller-saved) */

#define a1	$17

#define a2	$18

#define a3	$19

#define a4	$20

#define a5	$21

#define t8	$22	/* more temps (caller-saved) */

#define t9	$23

#define t10	$24

#define t11	$25

#define ra	$26	/* return address register */

#define t12	$27

#define pv	t12	/* procedure-variable register */

#define AT	$at	/* assembler temporary */

#define gp	$29	/* global pointer */

#define sp	$30	/* stack pointer */

#define zero	$31	/* reads as zero, writes are noops */

#endif /* _UAPI_ASM_SW64_REGDEF_H */