Commit 767cc050 authored by Mark Brown's avatar Mark Brown Committed by Marc Zyngier
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KVM: selftests: Comment newly defined aarch64 ID registers 



All otherwise unspecified aarch64 ID registers should be read as zero so
we cover the whole ID register space in the get-reg-list test but we've
added comments for those that have been named. Add comments for
ID_AA64PFR2_EL1, ID_AA64SMFR0_EL1, ID_AA64ISAR2_EL1, ID_AA64MMFR3_EL1
and ID_AA64MMFR4_EL1 which have been defined since the comments were
added so someone looking for them will see that they are covered.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230210-kvm-arm64-getreg-comments-v1-1-a16c73be5ab4@kernel.org
parent e8d018dd

tools/testing/selftests/kvm/aarch64/get-reg-list.c

+5 −5
Original line number Diff line number Diff line
@@ -807,10 +807,10 @@ static __u64 base_regs[] = { 
	ARM64_SYS_REG(3, 0, 0, 3, 7),

	ARM64_SYS_REG(3, 0, 0, 4, 0),	/* ID_AA64PFR0_EL1 */

	ARM64_SYS_REG(3, 0, 0, 4, 1),	/* ID_AA64PFR1_EL1 */

	ARM64_SYS_REG(3, 0, 0, 4, 2),

	ARM64_SYS_REG(3, 0, 0, 4, 2),	/* ID_AA64PFR2_EL1 */

	ARM64_SYS_REG(3, 0, 0, 4, 3),

	ARM64_SYS_REG(3, 0, 0, 4, 4),	/* ID_AA64ZFR0_EL1 */

	ARM64_SYS_REG(3, 0, 0, 4, 5),

	ARM64_SYS_REG(3, 0, 0, 4, 5),	/* ID_AA64SMFR0_EL1 */

	ARM64_SYS_REG(3, 0, 0, 4, 6),

	ARM64_SYS_REG(3, 0, 0, 4, 7),

	ARM64_SYS_REG(3, 0, 0, 5, 0),	/* ID_AA64DFR0_EL1 */
@@ -823,7 +823,7 @@ static __u64 base_regs[] = { 
	ARM64_SYS_REG(3, 0, 0, 5, 7),

	ARM64_SYS_REG(3, 0, 0, 6, 0),	/* ID_AA64ISAR0_EL1 */

	ARM64_SYS_REG(3, 0, 0, 6, 1),	/* ID_AA64ISAR1_EL1 */

	ARM64_SYS_REG(3, 0, 0, 6, 2),

	ARM64_SYS_REG(3, 0, 0, 6, 2),	/* ID_AA64ISAR2_EL1 */

	ARM64_SYS_REG(3, 0, 0, 6, 3),

	ARM64_SYS_REG(3, 0, 0, 6, 4),

	ARM64_SYS_REG(3, 0, 0, 6, 5),
@@ -832,8 +832,8 @@ static __u64 base_regs[] = { 
	ARM64_SYS_REG(3, 0, 0, 7, 0),	/* ID_AA64MMFR0_EL1 */

	ARM64_SYS_REG(3, 0, 0, 7, 1),	/* ID_AA64MMFR1_EL1 */

	ARM64_SYS_REG(3, 0, 0, 7, 2),	/* ID_AA64MMFR2_EL1 */

	ARM64_SYS_REG(3, 0, 0, 7, 3),

	ARM64_SYS_REG(3, 0, 0, 7, 4),

	ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */

	ARM64_SYS_REG(3, 0, 0, 7, 4),	/* ID_AA64MMFR4_EL1 */

	ARM64_SYS_REG(3, 0, 0, 7, 5),

	ARM64_SYS_REG(3, 0, 0, 7, 6),

	ARM64_SYS_REG(3, 0, 0, 7, 7),