Commit 7649a5d1 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xehp: Annotate a couple more workaround registers as MCR 



GAMSTLB_CTRL and GAMCNTRL_CTRL became multicast/replicated registers on
Xe_HP.  They should be defined accordingly and use MCR-aware operations.

These registers have only been used for some dg2/xehpsdv workarounds, so
this fix is mostly just for consistency/future-proofing; even lacking
the MCR annotation, workarounds will always be properly applied in a
multicast manner on these platforms.

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Fixes: 58bc2453 ("drm/i915: Define multicast registers as a new type")
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230125234159.3015385-3-matthew.d.roper@intel.com
parent eda94a6e

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+2 −2
Original line number Diff line number Diff line
@@ -1107,12 +1107,12 @@ 
#define XELPMP_VEBX_MOD_CTRL			_MMIO(0xcf38)

#define   FORCE_MISS_FTLB			REG_BIT(3)



#define GEN12_GAMSTLB_CTRL			_MMIO(0xcf4c)

#define XEHP_GAMSTLB_CTRL			MCR_REG(0xcf4c)

#define   CONTROL_BLOCK_CLKGATE_DIS		REG_BIT(12)

#define   EGRESS_BLOCK_CLKGATE_DIS		REG_BIT(11)

#define   TAG_BLOCK_CLKGATE_DIS			REG_BIT(7)



#define GEN12_GAMCNTRL_CTRL			_MMIO(0xcf54)

#define XEHP_GAMCNTRL_CTRL			MCR_REG(0xcf54)

#define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)

#define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+8 −8
Original line number Diff line number Diff line
@@ -1564,7 +1564,7 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
	wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);



	/* Wa_14014368820:xehpsdv */

	wa_write_or(wal, GEN12_GAMCNTRL_CTRL,

	wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,

			INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);

}
@@ -1659,7 +1659,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
		wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);



		/* Wa_14010680813:dg2_g10 */

		wa_write_or(wal, GEN12_GAMSTLB_CTRL,

		wa_mcr_write_or(wal, XEHP_GAMSTLB_CTRL,

				CONTROL_BLOCK_CLKGATE_DIS |

				EGRESS_BLOCK_CLKGATE_DIS |

				TAG_BLOCK_CLKGATE_DIS);
@@ -1685,7 +1685,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
	wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);



	/* Wa_1509235366:dg2 */

	wa_write_or(wal, GEN12_GAMCNTRL_CTRL,

	wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,

			INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);

}