Commit 763e13f2 authored by Fabien Parent's avatar Fabien Parent Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: mt8167: add power domains 



Add support for the MT8167 power domains.

Signed-off-by: default avatarFabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210405172836.2038526-1-fparent@baylibre.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent e6f73028

arch/arm64/boot/dts/mediatek/mt8167.dtsi

+68 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <dt-bindings/clock/mt8167-clk.h>

#include <dt-bindings/memory/mt8167-larb-port.h>

#include <dt-bindings/power/mt8167-power.h>



#include "mt8167-pinfunc.h"
@@ -34,6 +35,73 @@ 
			#clock-cells = <1>;

		};



		scpsys: syscon@10006000 {

			compatible = "syscon", "simple-mfd";

			reg = <0 0x10006000 0 0x1000>;

			#power-domain-cells = <1>;



			spm: power-controller {

				compatible = "mediatek,mt8167-power-controller";

				#address-cells = <1>;

				#size-cells = <0>;

				#power-domain-cells = <1>;



				/* power domains of the SoC */

				power-domain@MT8167_POWER_DOMAIN_MM {

					reg = <MT8167_POWER_DOMAIN_MM>;

					clocks = <&topckgen CLK_TOP_SMI_MM>;

					clock-names = "mm";

					#power-domain-cells = <0>;

					mediatek,infracfg = <&infracfg>;

				};



				power-domain@MT8167_POWER_DOMAIN_VDEC {

					reg = <MT8167_POWER_DOMAIN_VDEC>;

					clocks = <&topckgen CLK_TOP_SMI_MM>,

						 <&topckgen CLK_TOP_RG_VDEC>;

					clock-names = "mm", "vdec";

					#power-domain-cells = <0>;

				};



				power-domain@MT8167_POWER_DOMAIN_ISP {

					reg = <MT8167_POWER_DOMAIN_ISP>;

					clocks = <&topckgen CLK_TOP_SMI_MM>;

					clock-names = "mm";

					#power-domain-cells = <0>;

				};



				power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {

					reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;

					clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,

						 <&topckgen CLK_TOP_RG_SLOW_MFG>;

					clock-names = "axi_mfg", "mfg";

					#address-cells = <1>;

					#size-cells = <0>;

					#power-domain-cells = <1>;

					mediatek,infracfg = <&infracfg>;



					power-domain@MT8167_POWER_DOMAIN_MFG_2D {

						reg = <MT8167_POWER_DOMAIN_MFG_2D>;

						#address-cells = <1>;

						#size-cells = <0>;

						#power-domain-cells = <1>;



						power-domain@MT8167_POWER_DOMAIN_MFG {

							reg = <MT8167_POWER_DOMAIN_MFG>;

							#power-domain-cells = <0>;

							mediatek,infracfg = <&infracfg>;

						};

					};

				};



				power-domain@MT8167_POWER_DOMAIN_CONN {

					reg = <MT8167_POWER_DOMAIN_CONN>;

					#power-domain-cells = <0>;

					mediatek,infracfg = <&infracfg>;

				};

			};

		};



		imgsys: syscon@15000000 {

			compatible = "mediatek,mt8167-imgsys", "syscon";

			reg = <0 0x15000000 0 0x1000>;