Commit 76346cf7 authored by Imran Shaik's avatar Imran Shaik Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-qdu1000: Add support for GDSCs 



Add the GDSCs support for QDU1000 and QRU1000 SoCs.

Co-developed-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Signed-off-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Signed-off-by: default avatarImran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-7-quic_imrashai@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 089aad8c

drivers/clk/qcom/gcc-qdu1000.c

+42 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include "clk-regmap-divider.h"

#include "clk-regmap-mux.h"

#include "clk-regmap-phy-mux.h"

#include "gdsc.h"

#include "reset.h"



enum {
@@ -2409,6 +2410,39 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 
	},

};



static struct gdsc pcie_0_gdsc = {

	.gdscr = 0x9d004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "gcc_pcie_0_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

};



static struct gdsc pcie_0_phy_gdsc = {

	.gdscr = 0x7c004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0x2,

	.pd = {

		.name = "gcc_pcie_0_phy_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

};



static struct gdsc usb30_prim_gdsc = {

	.gdscr = 0x49004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "gcc_usb30_prim_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

};



static struct clk_regmap *gcc_qdu1000_clocks[] = {

	[GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr,

	[GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr,
@@ -2545,6 +2579,12 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { 
	[GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,

};



static struct gdsc *gcc_qdu1000_gdscs[] = {

	[PCIE_0_GDSC] = &pcie_0_gdsc,

	[PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,

	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,

};



static const struct qcom_reset_map gcc_qdu1000_resets[] = {

	[GCC_ECPRI_CC_BCR] = { 0x3e000 },

	[GCC_ECPRI_SS_BCR] = { 0x3a000 },
@@ -2606,6 +2646,8 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = { 
	.num_clks = ARRAY_SIZE(gcc_qdu1000_clocks),

	.resets = gcc_qdu1000_resets,

	.num_resets = ARRAY_SIZE(gcc_qdu1000_resets),

	.gdscs = gcc_qdu1000_gdscs,

	.num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs),

};



static const struct of_device_id gcc_qdu1000_match_table[] = {