Commit 761c629d authored by Kuogee Hsieh's avatar Kuogee Hsieh Committed by Dmitry Baryshkov
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drm/msm/dpu: separate DSC flush update out of interface 



Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same time to make it
consistent with the location of flush programming of other DPU sub-blocks.

Changes in v10:
-- rewording commit text
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- ctx->pending_dsc_flush_mask = 0;

Changes in v11:
-- add Fixes tag

Changes in v12:
-- move dsc parameter to next line at dpu_encoder_dsc_pipe_cfg()

Changes in v14:
-- Fixes tag had been move to 1st patch of this series

Signed-off-by: default avatarKuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/539506/
Link: https://lore.kernel.org/r/1685036458-22683-9-git-send-email-quic_khsieh@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 625cbb07

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+8 −2
Original line number Diff line number Diff line
@@ -1834,7 +1834,8 @@ dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, 
	return DIV_ROUND_UP(total_pixels, dsc->slice_width);

}



static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,

static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,

				     struct dpu_hw_dsc *hw_dsc,

				     struct dpu_hw_pingpong *hw_pp,

				     struct drm_dsc_config *dsc,

				     u32 common_mode,
@@ -1854,6 +1855,9 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc, 


	if (hw_pp->ops.enable_dsc)

		hw_pp->ops.enable_dsc(hw_pp);



	if (ctl->ops.update_pending_flush_dsc)

		ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);

}



static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
@@ -1861,6 +1865,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, 
{

	/* coding only for 2LM, 2enc, 1 dsc config */

	struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;

	struct dpu_hw_ctl *ctl = enc_master->hw_ctl;

	struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];

	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];

	int this_frame_slices;
@@ -1898,7 +1903,8 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, 
	initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);



	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)

		dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines);

		dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],

					 dsc, dsc_common_mode, initial_lines);

}



void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+17 −6
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) 
	ctx->pending_intf_flush_mask = 0;

	ctx->pending_wb_flush_mask = 0;

	ctx->pending_merge_3d_flush_mask = 0;

	ctx->pending_dsc_flush_mask = 0;



	memset(ctx->pending_dspp_flush_mask, 0,

		sizeof(ctx->pending_dspp_flush_mask));
@@ -142,6 +143,11 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) 
				CTL_DSPP_n_FLUSH(dspp - DSPP_0),

				ctx->pending_dspp_flush_mask[dspp - DSPP_0]);

		}



	if (ctx->pending_flush_mask & BIT(DSC_IDX))

		DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH,

			      ctx->pending_dsc_flush_mask);



	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);

}
@@ -288,6 +294,13 @@ static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx, 
	ctx->pending_flush_mask |= BIT(MERGE_3D_IDX);

}



static void dpu_hw_ctl_update_pending_flush_dsc_v1(struct dpu_hw_ctl *ctx,

						   enum dpu_dsc dsc_num)

{

	ctx->pending_dsc_flush_mask |= BIT(dsc_num - DSC_0);

	ctx->pending_flush_mask |= BIT(DSC_IDX);

}



static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,

	enum dpu_dspp dspp, u32 dspp_sub_blk)

{
@@ -499,9 +512,6 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, 
	if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))

		mode_sel = CTL_DEFAULT_GROUP_ID  << 28;



	if (cfg->dsc)

		DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);



	if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)

		mode_sel |= BIT(17);
@@ -521,11 +531,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, 
	if (cfg->merge_3d)

		DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,

			      BIT(cfg->merge_3d - MERGE_3D_0));

	if (cfg->dsc) {

		DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, BIT(DSC_IDX));



	if (cfg->dsc)

		DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);

}

}



static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,

		struct dpu_hw_intf_cfg *cfg)
@@ -627,6 +636,8 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, 
		ops->update_pending_flush_merge_3d =

			dpu_hw_ctl_update_pending_flush_merge_3d_v1;

		ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;

		ops->update_pending_flush_dsc =

			dpu_hw_ctl_update_pending_flush_dsc_v1;

	} else {

		ops->trigger_flush = dpu_hw_ctl_trigger_flush;

		ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

+11 −0
Original line number Diff line number Diff line
@@ -157,6 +157,15 @@ struct dpu_hw_ctl_ops { 
	void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx,

		enum dpu_dspp blk, u32 dspp_sub_blk);



	/**

	 * OR in the given flushbits to the cached pending_(dsc_)flush_mask

	 * No effect on hardware

	 * @ctx: ctl path ctx pointer

	 * @blk: interface block index

	 */

	void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx,

					 enum dpu_dsc blk);



	/**

	 * Write the value of the pending_flush_mask to hardware

	 * @ctx       : ctl path ctx pointer
@@ -229,6 +238,7 @@ struct dpu_hw_ctl_ops { 
 * @pending_flush_mask: storage for pending ctl_flush managed via ops

 * @pending_intf_flush_mask: pending INTF flush

 * @pending_wb_flush_mask: pending WB flush

 * @pending_dsc_flush_mask: pending DSC flush

 * @ops: operation list

 */

struct dpu_hw_ctl {
@@ -245,6 +255,7 @@ struct dpu_hw_ctl { 
	u32 pending_wb_flush_mask;

	u32 pending_merge_3d_flush_mask;

	u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];

	u32 pending_dsc_flush_mask;



	/* ops */

	struct dpu_hw_ctl_ops ops;