Commit 75b950ef authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Revert "drm/amd/display: Fix for otg synchronization logic" 

This reverts commit a896f870.

It causes odd flickering on my Radeon RX580 (PCI ID 1002:67df rev e7,
subsystem ID 1da2:e353).

Bisected right to this commit, and reverting it fixes things.

Link: https://lore.kernel.org/all/CAHk-=wg9hDde_L3bK9tAfdJ4N=TJJ+SjO3ZDONqH5=bVoy_Mzg@mail.gmail.com/


Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Jun Lei <Jun.Lei@amd.com>
Cc: Mustapha Ghaddar <mustapha.ghaddar@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: meenakshikumar somasundaram <meenakshikumar.somasundaram@amd.com>
Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 8d0749b4

drivers/gpu/drm/amd/display/dc/core/dc.c

+14 −21
Original line number Diff line number Diff line
@@ -1404,29 +1404,22 @@ static void program_timing_sync( 
				status->timing_sync_info.master = false;



		}



		/* remove any other pipes that are already been synced */

		if (dc->config.use_pipe_ctx_sync_logic) {

			/* check pipe's syncd to decide which pipe to be removed */

			for (j = 1; j < group_size; j++) {

				if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {

					group_size--;

					pipe_set[j] = pipe_set[group_size];

					j--;

				} else

					/* link slave pipe's syncd with master pipe */

					pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;

			}

		} else {

			/* remove any other pipes by checking valid plane */

		/* remove any other unblanked pipes as they have already been synced */

		for (j = j + 1; j < group_size; j++) {

				if (pipe_set[j]->plane_state) {

			bool is_blanked;



			if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)

				is_blanked =

					pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);

			else

				is_blanked =

					pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);

			if (!is_blanked) {

				group_size--;

				pipe_set[j] = pipe_set[group_size];

				j--;

			}

		}

 		}



		if (group_size > 1) {

			if (sync_type == TIMING_SYNCHRONIZABLE) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+0 −54
Original line number Diff line number Diff line
@@ -3216,57 +3216,3 @@ struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt( 
	return hpo_dp_link_enc;

}

#endif
 


void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,

		struct dc_state *context)

{

	int i, j;

	struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;



	/* If pipe backend is reset, need to reset pipe syncd status */

	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		pipe_ctx_old =	&dc->current_state->res_ctx.pipe_ctx[i];

		pipe_ctx = &context->res_ctx.pipe_ctx[i];



		if (!pipe_ctx_old->stream)

			continue;



		if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)

			continue;



		if (!pipe_ctx->stream ||

				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {



			/* Reset all the syncd pipes from the disabled pipe */

			for (j = 0; j < dc->res_pool->pipe_count; j++) {

				pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];

				if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) ||

					!IS_PIPE_SYNCD_VALID(pipe_ctx_syncd))

					SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j);

			}

		}

	}

}



void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,

	struct dc_state *context,

	uint8_t disabled_master_pipe_idx)

{

	int i;

	struct pipe_ctx *pipe_ctx, *pipe_ctx_check;



	pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];

	if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||

		!IS_PIPE_SYNCD_VALID(pipe_ctx))

		SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);



	/* for the pipe disabled, check if any slave pipe exists and assert */

	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		pipe_ctx_check = &context->res_ctx.pipe_ctx[i];



		if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&

			IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx))

			DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",

				i, disabled_master_pipe_idx);

	}

}

drivers/gpu/drm/amd/display/dc/dc.h

+0 −1
Original line number Diff line number Diff line
@@ -344,7 +344,6 @@ struct dc_config { 
	uint8_t  vblank_alignment_max_frame_time_diff;

	bool is_asymmetric_memory;

	bool is_single_rank_dimm;

	bool use_pipe_ctx_sync_logic;

};



enum visual_confirm {

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+0 −8
Original line number Diff line number Diff line
@@ -1566,10 +1566,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
				&pipe_ctx->stream->audio_info);

	}



	/* make sure no pipes syncd to the pipe being enabled */

	if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)

		check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);



#if defined(CONFIG_DRM_AMD_DC_DCN)

	/* DCN3.1 FPGA Workaround

	 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
@@ -2301,10 +2297,6 @@ enum dc_status dce110_apply_ctx_to_hw( 
	enum dc_status status;

	int i;



	/* reset syncd pipes from disabled pipes */

	if (dc->config.use_pipe_ctx_sync_logic)

		reset_syncd_pipes_from_disabled_pipes(dc, context);



	/* Reset old context */

	/* look up the targets that have been removed since last commit */

	hws->funcs.reset_hw_ctx_wrap(dc, context);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

+0 −3
Original line number Diff line number Diff line
@@ -2260,9 +2260,6 @@ static bool dcn31_resource_construct( 
	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

	dc->caps.color.mpc.ocsc = 1;



	/* Use pipe context based otg sync logic */

	dc->config.use_pipe_ctx_sync_logic = true;



	/* read VBIOS LTTPR caps */

	{

		if (ctx->dc_bios->funcs->get_lttpr_caps) {