Commit 75b7ae29 authored by Dan Williams's avatar Dan Williams
Browse files

cxl/mem: Validate port connectivity before dvsec ranges 



In preparation for validating DVSEC ranges against the platform declared
CXL memory ranges (ACPI CFMWS) move port enumeration before the
endpoint's decoder validation. Ultimately this logic will move to the
port driver, but create a bisect point before that larger move.

Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291687749.1426646.18091538443879226995.stgit@dwillia2-xfh


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 76a4121e

drivers/cxl/mem.c

+16 −16
Original line number Diff line number Diff line
@@ -140,22 +140,6 @@ static int cxl_mem_probe(struct device *dev) 
	if (work_pending(&cxlmd->detach_work))

		return -EBUSY;



	rc = cxlds->wait_media_ready(cxlds);

	if (rc) {

		dev_err(dev, "Media not active (%d)\n", rc);

		return rc;

	}



	/*

	 * If DVSEC ranges are being used instead of HDM decoder registers there

	 * is no use in trying to manage those.

	 */

	if (!cxl_hdm_decode_init(cxlds)) {

		dev_err(dev,

			"Legacy range registers configuration prevents HDM operation.\n");

		return -EBUSY;

	}



	rc = devm_cxl_enumerate_ports(cxlmd);

	if (rc)

		return rc;
@@ -181,6 +165,22 @@ static int cxl_mem_probe(struct device *dev) 
	if (rc)

		return rc;



	rc = cxlds->wait_media_ready(cxlds);

	if (rc) {

		dev_err(dev, "Media not active (%d)\n", rc);

		return rc;

	}



	/*

	 * If DVSEC ranges are being used instead of HDM decoder registers there

	 * is no use in trying to manage those.

	 */

	if (!cxl_hdm_decode_init(cxlds)) {

		dev_err(dev,

			"Legacy range registers configuration prevents HDM operation.\n");

		return -EBUSY;

	}



	/*

	 * The kernel may be operating out of CXL memory on this device,

	 * there is no spec defined way to determine whether this device