Commit 757a2f36 authored by Kuogee Hsieh's avatar Kuogee Hsieh Committed by Dmitry Baryshkov
Browse files

drm/msm/dp: enable widebus feature for display port 



Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy chipsets
does not support this feature, this feature is enabled by setting
wide_bus_en flag to true within msm_dp_desc struct.

changes in v2:
-- remove compression related code from timing
-- remove op_info from  struct msm_drm_private
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp

Changes in v3:
-- split patch into 3 patches
-- enable widebus feature base on chip hardware revision

Changes in v5:
-- DP_INTF_CONFIG_DATABUS_WIDEN

Changes in v6:
-- static inline bool msm_dp_wide_bus_enable() in msm_drv.h

Changes in v7:
-- add Tested-by

Changes in v9:
-- add wide_bus_en to msm_dp_desc

Changes in v10:
-- add wide_bus_en boolean to dp_catalog struc to avoid passing it as parameter

Changes in v11:
-- add const to dp_catalog_hw_revision()
-- add const to msm_dp_wide_bus_available()

Changes in v12:
-- dp_catalog_hw_revision(const struct dp_catalog *dp_catalog)
-- msm_dp_wide_bus_available(const struct msm_dp *dp_display)

Signed-off-by: default avatarKuogee Hsieh <quic_khsieh@quicinc.com>
Reported-by: default avatarkernel test robot <lkp@intel.com>
Tested-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/476283/
Link: https://lore.kernel.org/r/1645824192-29670-5-git-send-email-quic_khsieh@quicinc.com


[DB: fixed the compilation]
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 3309a756

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+3 −0
Original line number Diff line number Diff line
@@ -2076,6 +2076,9 @@ int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, 
		timer_setup(&dpu_enc->vsync_event_timer,

				dpu_encoder_vsync_event_handler,

				0);

	else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS)

		dpu_enc->wide_bus_en = msm_dp_wide_bus_available(

				priv->dp[disp_info->h_tile_instance[0]]);



	INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,

			dpu_encoder_off_work);

drivers/gpu/drm/msm/dp/dp_catalog.c

+32 −2
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ 
#define DP_INTERRUPT_STATUS_ACK_SHIFT	1

#define DP_INTERRUPT_STATUS_MASK_SHIFT	2



#define DP_INTF_CONFIG_DATABUS_WIDEN     BIT(4)



#define DP_INTERRUPT_STATUS1 \

	(DP_INTR_AUX_I2C_DONE| \

	DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
@@ -80,7 +82,7 @@ static inline void dp_write_aux(struct dp_catalog_private *catalog, 
	writel(data, catalog->io->dp_controller.aux.base + offset);

}



static inline u32 dp_read_ahb(struct dp_catalog_private *catalog, u32 offset)

static inline u32 dp_read_ahb(const struct dp_catalog_private *catalog, u32 offset)

{

	return readl_relaxed(catalog->io->dp_controller.ahb.base + offset);

}
@@ -482,6 +484,22 @@ int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, 
	return 0;

}



/**

 * dp_catalog_hw_revision() - retrieve DP hw revision

 *

 * @dp_catalog: DP catalog structure

 *

 * Return: DP controller hw revision

 *

 */

u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog)

{

	const struct dp_catalog_private *catalog = container_of(dp_catalog,

				struct dp_catalog_private, dp_catalog);



	return dp_read_ahb(catalog, REG_DP_HW_VERSION);

}



/**

 * dp_catalog_ctrl_reset() - reset DP controller

 *
@@ -743,6 +761,7 @@ int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog) 
{

	struct dp_catalog_private *catalog = container_of(dp_catalog,

				struct dp_catalog_private, dp_catalog);

	u32 reg;



	dp_write_link(catalog, REG_DP_TOTAL_HOR_VER,

				dp_catalog->total);
@@ -751,7 +770,18 @@ int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog) 
	dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,

				dp_catalog->width_blanking);

	dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active);

	dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0);



	reg = dp_read_p0(catalog, MMSS_DP_INTF_CONFIG);



	if (dp_catalog->wide_bus_en)

		reg |= DP_INTF_CONFIG_DATABUS_WIDEN;

	else

		reg &= ~DP_INTF_CONFIG_DATABUS_WIDEN;





	DRM_DEBUG_DP("wide_bus_en=%d reg=%#x\n", dp_catalog->wide_bus_en, reg);



	dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg);

	return 0;

}

drivers/gpu/drm/msm/dp/dp_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ struct dp_catalog { 
	enum dp_catalog_audio_sdp_type sdp_type;

	enum dp_catalog_audio_header_type sdp_header;

	u32 audio_data;

	bool wide_bus_en;

};



/* Debug module */
@@ -95,6 +96,7 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); 
void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,

				u32 stream_rate_khz, bool fixed_nvid);

int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern);

u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog);

void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog);

bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog);

void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);

drivers/gpu/drm/msm/dp/dp_ctrl.c

+6 −1
Original line number Diff line number Diff line
@@ -1802,6 +1802,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) 
	int ret = 0;

	bool mainlink_ready = false;

	struct dp_ctrl_private *ctrl;

	unsigned long pixel_rate_orig;



	if (!dp_ctrl)

		return -EINVAL;
@@ -1810,6 +1811,10 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) 


	ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;



	pixel_rate_orig = ctrl->dp_ctrl.pixel_rate;

	if (dp_ctrl->wide_bus_en)

		ctrl->dp_ctrl.pixel_rate >>= 1;



	DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",

		ctrl->link->link_params.rate,

		ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
@@ -1849,7 +1854,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) 


	dp_catalog_ctrl_config_msa(ctrl->catalog,

		ctrl->link->link_params.rate,

		ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl));

		pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl));



	dp_ctrl_setup_tr_unit(ctrl);

drivers/gpu/drm/msm/dp/dp_ctrl.h

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ struct dp_ctrl { 
	bool orientation;

	atomic_t aborted;

	u32 pixel_rate;

	bool wide_bus_en;

};



int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl);