Commit 7557f58b authored by Marijn Suijten's avatar Marijn Suijten Committed by Abhinav Kumar
Browse files

drm/msm/dpu: Set PINGPONG block length to zero for DPU >= 7.0.0 



Despite downstream DTS stating otherwise, the PINGPONG block has no
registers starting with DPU revision 7.0.0.  TEAR registers are gone
since DPU 5.0.0 after being moved to the INTF block, and DSC registers
are gone since 7.0.0, leaving only the dither sub-block.

A future patch, part of the DSC 1.2 series, should disable DSC functions
on the PINGPONG block for all DPU >= 7.0.0 hardware.

Fixes: 4a352c2f ("drm/msm/dpu: Introduce SC8280XP")
Fixes: 0e91bcbb ("drm/msm/dpu: Add SM8350 to hw catalog")
Fixes: 100d7ef6 ("drm/msm/dpu: add support for SM8450")
Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/534206/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-7-27ce1a5ab5c6@somainline.org


Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
parent fe47a308

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

+6 −6
Original line number Diff line number Diff line
@@ -127,22 +127,22 @@ static const struct dpu_dspp_cfg sm8350_dspp[] = { 
};



static const struct dpu_pingpong_cfg sm8350_pp[] = {

	PP_BLK("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),

	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),

	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),

	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),

	PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

			-1),

	PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

			-1),

};

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

+4 −4
Original line number Diff line number Diff line
@@ -87,10 +87,10 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = { 
};



static const struct dpu_pingpong_cfg sc7280_pp[] = {

	PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1),

	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),

	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),

	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),

	PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1),

	PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),

	PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),

	PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),

};



static const struct dpu_intf_cfg sc7280_intf[] = {

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

+6 −6
Original line number Diff line number Diff line
@@ -121,17 +121,17 @@ static const struct dpu_dspp_cfg sc8280xp_dspp[] = { 
};



static const struct dpu_pingpong_cfg sc8280xp_pp[] = {

	PP_BLK("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),

	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),

	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),

	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),

	PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),

	PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),

};

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

+8 −8
Original line number Diff line number Diff line
@@ -128,28 +128,28 @@ static const struct dpu_dspp_cfg sm8450_dspp[] = { 
};

/* FIXME: interrupts */

static const struct dpu_pingpong_cfg sm8450_pp[] = {

	PP_BLK("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),

	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),

	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),

	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),

	PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),

			-1),

	PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,

			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),

			-1),

	PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sc7280_pp_sblk,

			-1,

			-1),

	PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sc7280_pp_sblk,

	PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sc7280_pp_sblk,

			-1,

			-1),

};