Commit 754c4050 authored by Florian Fainelli's avatar Florian Fainelli
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ARM: dts: BCM5301X: Fix I2C controller interrupt 



The I2C interrupt controller line is off by 32 because the datasheet
describes interrupt inputs into the GIC which are for Shared Peripheral
Interrupts and are starting at offset 32. The ARM GIC binding expects
the SPI interrupts to be numbered from 0 relative to the SPI base.

Fixes: bb097e3e ("ARM: dts: BCM5301X: Add I2C support to the DT")
Tested-by: default avatarChristian Lamparter <chunkeey@gmail.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent fa55b7dc

arch/arm/boot/dts/bcm5301x.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -408,7 +408,7 @@ 
	i2c0: i2c@18009000 {

		compatible = "brcm,iproc-i2c";

		reg = <0x18009000 0x50>;

		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-frequency = <100000>;