Commit 751f204a authored by Miquel Raynal's avatar Miquel Raynal
Browse files

dt-bindings: mtd: nand-chip: Create a NAND chip description 



Move the NAND chip description out of the NAND controller file. Indeed,
a subsequent part of the properties supported by a raw NAND chip are
also supported by SPI-NAND chips. So let's create a generic NAND chip
description which will be pulled by nand-controller.yaml and later by
spi-nand.yaml as well.

Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-5-miquel.raynal@bootlin.com
parent f0dcb5bd

Documentation/devicetree/bindings/mtd/nand-chip.yaml

0 → 100644
+70 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/nand-chip.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NAND Chip and NAND Controller Generic Binding



maintainers:

  - Miquel Raynal <miquel.raynal@bootlin.com>



description: |

  This file covers the generic description of a NAND chip. It implies that the

  bus interface should not be taken into account: both raw NAND devices and

  SPI-NAND devices are concerned by this description.



properties:

  reg:

    description:

      Contains the chip-select IDs.



  nand-ecc-engine:

    description: |

      A phandle on the hardware ECC engine if any. There are

      basically three possibilities:

      1/ The ECC engine is part of the NAND controller, in this

      case the phandle should reference the parent node.

      2/ The ECC engine is part of the NAND part (on-die), in this

      case the phandle should reference the node itself.

      3/ The ECC engine is external, in this case the phandle should

      reference the specific ECC engine node.

    $ref: /schemas/types.yaml#/definitions/phandle



  nand-use-soft-ecc-engine:

    description: Use a software ECC engine.

    type: boolean



  nand-no-ecc-engine:

    description: Do not use any ECC correction.

    type: boolean



  nand-ecc-algo:

    description:

      Desired ECC algorithm.

    $ref: /schemas/types.yaml#/definitions/string

    enum: [hamming, bch, rs]



  nand-ecc-strength:

    description:

      Maximum number of bits that can be corrected per ECC step.

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1



  nand-ecc-step-size:

    description:

      Number of data bytes covered by a single ECC step.

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1



  secure-regions:

    description:

      Regions in the NAND chip which are protected using a secure element

      like Trustzone. This property contains the start address and size of

      the secure regions present.

    $ref: /schemas/types.yaml#/definitions/uint64-matrix



required:

  - reg



additionalProperties: true

Documentation/devicetree/bindings/mtd/nand-controller.yaml

+2 −48
Original line number Diff line number Diff line
@@ -52,31 +52,13 @@ properties: 
patternProperties:

  "^nand@[a-f0-9]$":

    type: object

    $ref: "nand-chip.yaml#"



    properties:

      reg:

        description:

          Contains the chip-select IDs.



      nand-ecc-engine:

        description: |

          A phandle on the hardware ECC engine if any. There are

          basically three possibilities:

          1/ The ECC engine is part of the NAND controller, in this

          case the phandle should reference the parent node.

          2/ The ECC engine is part of the NAND part (on-die), in this

          case the phandle should reference the node itself.

          3/ The ECC engine is external, in this case the phandle should

          reference the specific ECC engine node.

        $ref: /schemas/types.yaml#/definitions/phandle



      nand-use-soft-ecc-engine:

        description: Use a software ECC engine.

        type: boolean



      nand-no-ecc-engine:

        description: Do not use any ECC correction.

        type: boolean



      nand-ecc-placement:

        description:

          Location of the ECC bytes. This location is unknown by default
@@ -86,12 +68,6 @@ patternProperties: 
        $ref: /schemas/types.yaml#/definitions/string

        enum: [ oob, interleaved ]



      nand-ecc-algo:

        description:

          Desired ECC algorithm.

        $ref: /schemas/types.yaml#/definitions/string

        enum: [hamming, bch, rs]



      nand-bus-width:

        description:

          Bus width to the NAND chip
@@ -110,18 +86,6 @@ patternProperties: 
          build a volatile BBT in RAM.

        $ref: /schemas/types.yaml#/definitions/flag



      nand-ecc-strength:

        description:

          Maximum number of bits that can be corrected per ECC step.

        $ref: /schemas/types.yaml#/definitions/uint32

        minimum: 1



      nand-ecc-step-size:

        description:

          Number of data bytes covered by a single ECC step.

        $ref: /schemas/types.yaml#/definitions/uint32

        minimum: 1



      nand-ecc-maximize:

        description:

          Whether or not the ECC strength should be maximized. The
@@ -152,13 +116,6 @@ patternProperties: 
          Ready/Busy pins. Active state refers to the NAND ready state and

          should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.



      secure-regions:

        description:

          Regions in the NAND chip which are protected using a secure element

          like Trustzone. This property contains the start address and size of

          the secure regions present.

        $ref: /schemas/types.yaml#/definitions/uint64-matrix



    required:

      - reg
@@ -179,9 +136,6 @@ examples: 


      nand@0 {

        reg = <0>; /* Native CS */

        nand-use-soft-ecc-engine;

        nand-ecc-algo = "bch";



        /* NAND chip specific properties */

      };