net: ll_temac: fix the format of block comments (75124116) · Commits · EulixOS / Software / Kernel

drivers/net/ethernet/xilinx/ll_temac.h

+95 −86

Original line number	Diff line number	Diff line
		@@ -21,36 +21,45 @@
		/* Configuration options */

		/* Accept all incoming packets.
		* This option defaults to disabled (cleared) */
		* This option defaults to disabled (cleared)
		*/
		#define XTE_OPTION_PROMISC (1 << 0)
		/* Jumbo frame support for Tx & Rx.
		* This option defaults to disabled (cleared) */
		* This option defaults to disabled (cleared)
		*/
		#define XTE_OPTION_JUMBO (1 << 1)
		/* VLAN Rx & Tx frame support.
		* This option defaults to disabled (cleared) */
		* This option defaults to disabled (cleared)
		*/
		#define XTE_OPTION_VLAN (1 << 2)
		/* Enable recognition of flow control frames on Rx
		* This option defaults to enabled (set) */
		* This option defaults to enabled (set)
		*/
		#define XTE_OPTION_FLOW_CONTROL (1 << 4)
		/* Strip FCS and PAD from incoming frames.
		* Note: PAD from VLAN frames is not stripped.
		* This option defaults to disabled (set) */
		* This option defaults to disabled (set)
		*/
		#define XTE_OPTION_FCS_STRIP (1 << 5)
		/* Generate FCS field and add PAD automatically for outgoing frames.
		* This option defaults to enabled (set) */
		* This option defaults to enabled (set)
		*/
		#define XTE_OPTION_FCS_INSERT (1 << 6)
		/* Enable Length/Type error checking for incoming frames. When this option is
		set, the MAC will filter frames that have a mismatched type/length field
		and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
		types of frames are encountered. When this option is cleared, the MAC will
		allow these types of frames to be received.
		This option defaults to enabled (set) */
		* set, the MAC will filter frames that have a mismatched type/length field
		* and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
		* types of frames are encountered. When this option is cleared, the MAC will
		* allow these types of frames to be received.
		* This option defaults to enabled (set)
		*/
		#define XTE_OPTION_LENTYPE_ERR (1 << 7)
		/* Enable the transmitter.
		* This option defaults to enabled (set) */
		* This option defaults to enabled (set)
		*/
		#define XTE_OPTION_TXEN (1 << 11)
		/* Enable the receiver
		* This option defaults to enabled (set) */
		* This option defaults to enabled (set)
		*/
		#define XTE_OPTION_RXEN (1 << 12)

		/* Default options set when device is initialized or reset */
		@@ -68,17 +77,17 @@ This option defaults to enabled (set) */
		#define TX_TAILDESC_PTR 0x04 /* rw */
		#define TX_CHNL_CTRL 0x05 /* rw */
		/*
		0:7 24:31 IRQTimeout
		8:15 16:23 IRQCount
		16:20 11:15 Reserved
		21 10 0
		22 9 UseIntOnEnd
		23 8 LdIRQCnt
		24 7 IRQEn
		25:28 3:6 Reserved
		29 2 IrqErrEn
		30 1 IrqDlyEn
		31 0 IrqCoalEn
		* 0:7 24:31 IRQTimeout
		* 8:15 16:23 IRQCount
		* 16:20 11:15 Reserved
		* 21 10 0
		* 22 9 UseIntOnEnd
		* 23 8 LdIRQCnt
		* 24 7 IRQEn
		* 25:28 3:6 Reserved
		* 29 2 IrqErrEn
		* 30 1 IrqDlyEn
		* 31 0 IrqCoalEn
		*/
		#define CHNL_CTRL_IRQ_IOE (1 << 9)
		#define CHNL_CTRL_IRQ_EN (1 << 7)
		@@ -87,34 +96,34 @@ This option defaults to enabled (set) */
		#define CHNL_CTRL_IRQ_COAL_EN (1 << 0)
		#define TX_IRQ_REG 0x06 /* rw */
		/*
		0:7 24:31 DltTmrValue
		8:15 16:23 ClscCntrValue
		16:17 14:15 Reserved
		18:21 10:13 ClscCnt
		22:23 8:9 DlyCnt
		24:28 3::7 Reserved
		29 2 ErrIrq
		30 1 DlyIrq
		31 0 CoalIrq
		* 0:7 24:31 DltTmrValue
		* 8:15 16:23 ClscCntrValue
		* 16:17 14:15 Reserved
		* 18:21 10:13 ClscCnt
		* 22:23 8:9 DlyCnt
		* 24:28 3::7 Reserved
		* 29 2 ErrIrq
		* 30 1 DlyIrq
		* 31 0 CoalIrq
		*/
		#define TX_CHNL_STS 0x07 /* r */
		/*
		0:9 22:31 Reserved
		10 21 TailPErr
		11 20 CmpErr
		12 19 AddrErr
		13 18 NxtPErr
		14 17 CurPErr
		15 16 BsyWr
		16:23 8:15 Reserved
		24 7 Error
		25 6 IOE
		26 5 SOE
		27 4 Cmplt
		28 3 SOP
		29 2 EOP
		30 1 EngBusy
		31 0 Reserved
		* 0:9 22:31 Reserved
		* 10 21 TailPErr
		* 11 20 CmpErr
		* 12 19 AddrErr
		* 13 18 NxtPErr
		* 14 17 CurPErr
		* 15 16 BsyWr
		* 16:23 8:15 Reserved
		* 24 7 Error
		* 25 6 IOE
		* 26 5 SOE
		* 27 4 Cmplt
		* 28 3 SOP
		* 29 2 EOP
		* 30 1 EngBusy
		* 31 0 Reserved
		*/

		#define RX_NXTDESC_PTR 0x08 /* r */
		@@ -124,17 +133,17 @@ This option defaults to enabled (set) */
		#define RX_TAILDESC_PTR 0x0c /* rw */
		#define RX_CHNL_CTRL 0x0d /* rw */
		/*
		0:7 24:31 IRQTimeout
		8:15 16:23 IRQCount
		16:20 11:15 Reserved
		21 10 0
		22 9 UseIntOnEnd
		23 8 LdIRQCnt
		24 7 IRQEn
		25:28 3:6 Reserved
		29 2 IrqErrEn
		30 1 IrqDlyEn
		31 0 IrqCoalEn
		* 0:7 24:31 IRQTimeout
		* 8:15 16:23 IRQCount
		* 16:20 11:15 Reserved
		* 21 10 0
		* 22 9 UseIntOnEnd
		* 23 8 LdIRQCnt
		* 24 7 IRQEn
		* 25:28 3:6 Reserved
		* 29 2 IrqErrEn
		* 30 1 IrqDlyEn
		* 31 0 IrqCoalEn
		*/
		#define RX_IRQ_REG 0x0e /* rw */
		#define IRQ_COAL (1 << 0)
		@@ -142,12 +151,12 @@ This option defaults to enabled (set) */
		#define IRQ_ERR (1 << 2)
		#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */
		/*
		0:7 24:31 DltTmrValue
		8:15 16:23 ClscCntrValue
		16:17 14:15 Reserved
		18:21 10:13 ClscCnt
		22:23 8:9 DlyCnt
		24:28 3::7 Reserved
		* 0:7 24:31 DltTmrValue
		* 8:15 16:23 ClscCntrValue
		* 16:17 14:15 Reserved
		* 18:21 10:13 ClscCnt
		* 22:23 8:9 DlyCnt
		* 24:28 3::7 Reserved
		*/
		#define RX_CHNL_STS 0x0f /* r */
		#define CHNL_STS_ENGBUSY (1 << 1)
		@@ -165,22 +174,22 @@ This option defaults to enabled (set) */
		#define CHNL_STS_CMPERR (1 << 20)
		#define CHNL_STS_TAILERR (1 << 21)
		/*
		0:9 22:31 Reserved
		10 21 TailPErr
		11 20 CmpErr
		12 19 AddrErr
		13 18 NxtPErr
		14 17 CurPErr
		15 16 BsyWr
		16:23 8:15 Reserved
		24 7 Error
		25 6 IOE
		26 5 SOE
		27 4 Cmplt
		28 3 SOP
		29 2 EOP
		30 1 EngBusy
		31 0 Reserved
		* 0:9 22:31 Reserved
		* 10 21 TailPErr
		* 11 20 CmpErr
		* 12 19 AddrErr
		* 13 18 NxtPErr
		* 14 17 CurPErr
		* 15 16 BsyWr
		* 16:23 8:15 Reserved
		* 24 7 Error
		* 25 6 IOE
		* 26 5 SOE
		* 27 4 Cmplt
		* 28 3 SOP
		* 29 2 EOP
		* 30 1 EngBusy
		* 31 0 Reserved
		*/

		#define DMA_CONTROL_REG 0x10 /* rw */

drivers/net/ethernet/xilinx/ll_temac_main.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -430,7 +430,8 @@ static void temac_do_set_mac_address(struct net_device *ndev)
		(ndev->dev_addr[2] << 16) \|
		(ndev->dev_addr[3] << 24));
		/* There are reserved bits in EUAW1
		* so don't affect them Set MAC bits [47:32] in EUAW1 */
		* so don't affect them Set MAC bits [47:32] in EUAW1
		*/
		temac_indirect_out32_locked(lp, XTE_UAW1_OFFSET,
		(ndev->dev_addr[4] & 0x000000ff) \|
		(ndev->dev_addr[5] << 8));
		@@ -691,7 +692,8 @@ static void temac_device_reset(struct net_device *ndev)
		spin_unlock_irqrestore(lp->indirect_lock, flags);

		/* Sync default options with HW
		* but leave receiver and transmitter disabled. */
		* but leave receiver and transmitter disabled.
		*/
		temac_setoptions(ndev,
		lp->options & ~(XTE_OPTION_TXEN \| XTE_OPTION_RXEN));

drivers/net/ethernet/xilinx/ll_temac_mdio.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -29,7 +29,8 @@ static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg)

		/* Write the PHY address to the MIIM Access Initiator register.
		* When the transfer completes, the PHY register value will appear
		* in the LSW0 register */
		* in the LSW0 register
		*/
		spin_lock_irqsave(lp->indirect_lock, flags);
		temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) \| reg);
		rc = temac_indirect_in32_locked(lp, XTE_MIIMAI_OFFSET);
		@@ -88,7 +89,8 @@ int temac_mdio_setup(struct temac_local lp, struct platform_device pdev)
		}

		/* Enable the MDIO bus by asserting the enable bit and writing
		* in the clock config */
		* in the clock config
		*/
		temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 \| clk_div);

		bus = devm_mdiobus_alloc(&pdev->dev);