Unverified Commit 7505576d authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer Committed by Paul Burton
Browse files

MIPS: add support for SGI Octane (IP30) 



This changeset adds support for SGI Octane/Octane2 workstations.

Signed-off-by: default avatarThomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: default avatarPaul Burton <paulburton@kernel.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
parent b9e9defb

arch/mips/Kbuild.platforms

+1 −0
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@@ -31,6 +31,7 @@ platforms += ralink 
platforms += rb532

platforms += sgi-ip22

platforms += sgi-ip27

platforms += sgi-ip30

platforms += sgi-ip32

platforms += sibyte

platforms += sni

arch/mips/Kconfig

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@@ -755,6 +755,33 @@ config SGI_IP28 
	  This is the SGI Indigo2 with R10000 processor.  To compile a Linux

	  kernel that runs on these, say Y here.



config SGI_IP30

	bool "SGI IP30 (Octane/Octane2)"

	select ARCH_HAS_PHYS_TO_DMA

	select FW_ARC

	select FW_ARC64

	select BOOT_ELF64

	select CEVT_R4K

	select CSRC_R4K

	select SYNC_R4K if SMP

	select ZONE_DMA32

	select HAVE_PCI

	select IRQ_MIPS_CPU

	select IRQ_DOMAIN_HIERARCHY

	select NR_CPUS_DEFAULT_2

	select PCI_DRIVERS_GENERIC

	select PCI_XTALK_BRIDGE

	select SYS_HAS_EARLY_PRINTK

	select SYS_HAS_CPU_R10000

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_SMP

	select MIPS_L1_CACHE_SHIFT_7

	select ARC_MEMORY

	help

	  These are the SGI Octane and Octane2 graphics workstations.  To

	  compile a Linux kernel that runs on these, say Y here.



config SGI_IP32

	bool "SGI IP32 (O2)"

	select ARC_MEMORY

arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * IP30/Octane cpu-features overrides.

 *

 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>

 *		 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>

 *		 2009 Johannes Dickgreber <tanzy@gmx.de>

 *		 2015 Joshua Kinard <kumba@gentoo.org>

 *

 */

#ifndef __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H

#define __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H



#include <asm/cpu.h>



/*

 * IP30 only supports R1[024]000 processors, all using the same config

 */

#define cpu_has_tlb			1

#define cpu_has_tlbinv			0

#define cpu_has_segments		0

#define cpu_has_eva			0

#define cpu_has_htw			0

#define cpu_has_rixiex			0

#define cpu_has_maar			0

#define cpu_has_rw_llb			0

#define cpu_has_3kex			0

#define cpu_has_4kex			1

#define cpu_has_3k_cache		0

#define cpu_has_4k_cache		1

#define cpu_has_6k_cache		0

#define cpu_has_8k_cache		0

#define cpu_has_tx39_cache		0

#define cpu_has_fpu			1

#define cpu_has_nofpuex			0

#define cpu_has_32fpr			1

#define cpu_has_counter			1

#define cpu_has_watch			1

#define cpu_has_64bits			1

#define cpu_has_divec			0

#define cpu_has_vce			0

#define cpu_has_cache_cdex_p		0

#define cpu_has_cache_cdex_s		0

#define cpu_has_prefetch		1

#define cpu_has_mcheck			0

#define cpu_has_ejtag			0

#define cpu_has_llsc			1

#define cpu_has_mips16			0

#define cpu_has_mdmx			0

#define cpu_has_mips3d			0

#define cpu_has_smartmips		0

#define cpu_has_rixi			0

#define cpu_has_xpa			0

#define cpu_has_vtag_icache		0

#define cpu_has_dc_aliases		0

#define cpu_has_ic_fills_f_dc		0



#define cpu_icache_snoops_remote_store	1



#define cpu_has_mips32r1		0

#define cpu_has_mips32r2		0

#define cpu_has_mips64r1		0

#define cpu_has_mips64r2		0

#define cpu_has_mips32r6		0

#define cpu_has_mips64r6		0



#define cpu_has_dsp			0

#define cpu_has_dsp2			0

#define cpu_has_mipsmt			0

#define cpu_has_userlocal		0

#define cpu_has_inclusive_pcaches	1

#define cpu_hwrena_impl_bits		0

#define cpu_has_perf_cntr_intr_bit	0

#define cpu_has_vz			0

#define cpu_has_fre			0

#define cpu_has_cdmm			0



#define cpu_dcache_line_size()		32

#define cpu_icache_line_size()		64

#define cpu_scache_line_size()		128



#endif /* __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/asm/mach-ip30/irq.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * HEART IRQ defines

 *

 * Copyright (C) 2009 Johannes Dickgreber <tanzy@gmx.de>

 *		 2014-2016 Joshua Kinard <kumba@gentoo.org>

 *

 */



#ifndef __ASM_MACH_IP30_IRQ_H

#define __ASM_MACH_IP30_IRQ_H



/*

 * HEART has 64 hardware interrupts, but use 128 to leave room for a few

 * software interrupts as well (such as the CPU timer interrupt.

 */

#define NR_IRQS				128



extern void __init ip30_install_ipi(void);



/*

 * HEART has 64 interrupt vectors available to it, subdivided into five

 * priority levels.  They are numbered 0 to 63.

 */

#define HEART_NUM_IRQS			64



/*

 * These are the five interrupt priority levels and their corresponding

 * CPU IPx interrupt pins.

 *

 * Level 4 - Error Interrupts.

 * Level 3 - HEART timer interrupt.

 * Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.

 * Level 1 - General device interrupts.

 * Level 0 - General device GFX flow control interrupts.

 */

#define HEART_L4_INT_MASK		0xfff8000000000000ULL	/* IP6 */

#define HEART_L3_INT_MASK		0x0004000000000000ULL	/* IP5 */

#define HEART_L2_INT_MASK		0x0003ffff00000000ULL	/* IP4 */

#define HEART_L1_INT_MASK		0x00000000ffff0000ULL	/* IP3 */

#define HEART_L0_INT_MASK		0x000000000000ffffULL	/* IP2 */



/* HEART L0 Interrupts (Low Priority) */

#define HEART_L0_INT_GENERIC		 0

#define HEART_L0_INT_FLOW_CTRL_HWTR_0	 1

#define HEART_L0_INT_FLOW_CTRL_HWTR_1	 2



/* HEART L2 Interrupts (High Priority) */

#define HEART_L2_INT_RESCHED_CPU_0	46

#define HEART_L2_INT_RESCHED_CPU_1	47

#define HEART_L2_INT_CALL_CPU_0		48

#define HEART_L2_INT_CALL_CPU_1		49



/* HEART L3 Interrupts (Compare/Counter Timer) */

#define HEART_L3_INT_TIMER		50



/* HEART L4 Interrupts (Errors) */

#define HEART_L4_INT_XWID_ERR_9		51

#define HEART_L4_INT_XWID_ERR_A		52

#define HEART_L4_INT_XWID_ERR_B		53

#define HEART_L4_INT_XWID_ERR_C		54

#define HEART_L4_INT_XWID_ERR_D		55

#define HEART_L4_INT_XWID_ERR_E		56

#define HEART_L4_INT_XWID_ERR_F		57

#define HEART_L4_INT_XWID_ERR_XBOW	58

#define HEART_L4_INT_CPU_BUS_ERR_0	59

#define HEART_L4_INT_CPU_BUS_ERR_1	60

#define HEART_L4_INT_CPU_BUS_ERR_2	61

#define HEART_L4_INT_CPU_BUS_ERR_3	62

#define HEART_L4_INT_HEART_EXCP		63



/*

 * Power Switch is wired via BaseIO BRIDGE slot #6.

 *

 * ACFail is wired via BaseIO BRIDGE slot #7.

 */

#define IP30_POWER_IRQ		HEART_L2_INT_POWER_BTN



#include_next <irq.h>



#define IP30_HEART_L0_IRQ	(MIPS_CPU_IRQ_BASE + 2)

#define IP30_HEART_L1_IRQ	(MIPS_CPU_IRQ_BASE + 3)

#define IP30_HEART_L2_IRQ	(MIPS_CPU_IRQ_BASE + 4)

#define IP30_HEART_TIMER_IRQ	(MIPS_CPU_IRQ_BASE + 5)

#define IP30_HEART_ERR_IRQ	(MIPS_CPU_IRQ_BASE + 6)



#endif /* __ASM_MACH_IP30_IRQ_H */

arch/mips/include/asm/mach-ip30/kernel-entry-init.h

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/* SPDX-License-Identifier: GPL-2.0 */



#ifndef __ASM_MACH_IP30_KERNEL_ENTRY_H

#define __ASM_MACH_IP30_KERNEL_ENTRY_H



	.macro  kernel_entry_setup

	.endm



	.macro	smp_slave_setup

	move	gp, a0

	.endm



#endif /* __ASM_MACH_IP30_KERNEL_ENTRY_H */