Commit 74fa4c81 authored by Saaem Rizvi's avatar Saaem Rizvi Committed by Alex Deucher
Browse files

drm/amd/display: Implement workaround for writing to OTG_PIXEL_RATE_DIV register 



[Why and How]
Current implementation requires FPGA builds to take a different
code path from DCN32 to write to OTG_PIXEL_RATE_DIV. Now that
we have a workaround to write to OTG_PIXEL_RATE_DIV register without
blanking display on hotplug on DCN32, we can allow the code paths for
FPGA to be exactly the same allowing for more consistent
testing.

Reviewed-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarSaaem Rizvi <SyedSaaem.Rizvi@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cfa07598

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h

+2 −1
Original line number Diff line number Diff line
@@ -230,7 +230,8 @@ 
	type DTBCLK_P2_SRC_SEL;\

	type DTBCLK_P2_EN;\

	type DTBCLK_P3_SRC_SEL;\

	type DTBCLK_P3_EN;

	type DTBCLK_P3_EN;\

	type DENTIST_DISPCLK_CHG_DONE;



struct dccg_shift {

	DCCG_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c

+22 −0
Original line number Diff line number Diff line
@@ -42,6 +42,20 @@ 
#define DC_LOGGER \

	dccg->ctx->logger



/* This function is a workaround for writing to OTG_PIXEL_RATE_DIV

 * without the probability of causing a DIG FIFO error.

 */

static void dccg32_wait_for_dentist_change_done(

	struct dccg *dccg)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);



	REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);

	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

}



static void dccg32_get_pixel_rate_div(

		struct dccg *dccg,

		uint32_t otg_inst,
@@ -110,21 +124,29 @@ static void dccg32_set_pixel_rate_div( 
		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,

				OTG0_PIXEL_RATE_DIVK1, k1,

				OTG0_PIXEL_RATE_DIVK2, k2);



		dccg32_wait_for_dentist_change_done(dccg);

		break;

	case 1:

		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,

				OTG1_PIXEL_RATE_DIVK1, k1,

				OTG1_PIXEL_RATE_DIVK2, k2);



		dccg32_wait_for_dentist_change_done(dccg);

		break;

	case 2:

		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,

				OTG2_PIXEL_RATE_DIVK1, k1,

				OTG2_PIXEL_RATE_DIVK2, k2);



		dccg32_wait_for_dentist_change_done(dccg);

		break;

	case 3:

		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,

				OTG3_PIXEL_RATE_DIVK1, k1,

				OTG3_PIXEL_RATE_DIVK2, k2);



		dccg32_wait_for_dentist_change_done(dccg);

		break;

	default:

		BREAK_TO_DEBUGGER();

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h

+2 −1
Original line number Diff line number Diff line
@@ -111,7 +111,8 @@ 
	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\

	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\

	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\

	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh)

	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\

	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)





struct dccg *dccg32_create(

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -1111,7 +1111,7 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign 
			*k2_div = PIXEL_RATE_DIV_BY_2;

		else

			*k2_div = PIXEL_RATE_DIV_BY_4;

	} else if (dc_is_dp_signal(stream->signal)) {

	} else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) {

		if (two_pix_per_container) {

			*k1_div = PIXEL_RATE_DIV_BY_1;

			*k2_div = PIXEL_RATE_DIV_BY_2;

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h

+2 −1
Original line number Diff line number Diff line
@@ -1276,7 +1276,8 @@ double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *conte 
      DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1),        \

      DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3),        \

      SR(DCCG_AUDIO_DTBCLK_DTO_MODULO), SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),       \

      SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL), SR(DCCG_AUDIO_DTO_SOURCE)     \

      SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL),                               \

      SR(DCCG_AUDIO_DTO_SOURCE), SR(DENTIST_DISPCLK_CNTL)                      \

  )



/* VMID */