Commit 74e38462 authored by zhuyikai's avatar zhuyikai Committed by s00851154
Browse files

net/hinic3: Support new TX feature 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IB6TTO?from=project-issue


CVE: NA

--------------------------------

Support new TX WQE offload format.

Signed-off-by: default avatarzhuyikai <zhuyikai1@h-partners.com>
parent e5f9cb08

drivers/net/ethernet/huawei/hinic3/hinic3_main.c

+8 −0
Original line number Diff line number Diff line
@@ -393,6 +393,14 @@ static void hinic3_free_txrxqs(struct hinic3_nic_dev *nic_dev) 


static void hinic3_tx_rx_ops_init(struct hinic3_nic_dev *nic_dev)

{

	if (HINIC3_SUPPORT_TX_COMPACT_WQE_OL(nic_dev->hwdev)) {

		nic_dev->tx_rx_ops.tx_set_wqebb_cnt = hinic3_tx_set_compact_offload_wqebb_cnt;

		nic_dev->tx_rx_ops.tx_set_wqe_task = hinic3_tx_set_compact_offload_wqe_task;

	} else {

		nic_dev->tx_rx_ops.tx_set_wqebb_cnt = hinic3_tx_set_wqebb_cnt;

		nic_dev->tx_rx_ops.tx_set_wqe_task = hinic3_tx_set_wqe_task;

	}



	if (HINIC3_SUPPORT_RX_COMPACT_CQE(nic_dev->hwdev))

		nic_dev->tx_rx_ops.rx_get_cqe_info = hinic3_rx_get_compact_cqe_info;

	else

drivers/net/ethernet/huawei/hinic3/hinic3_mgmt_interface.h

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ enum nic_feature_cap { 
	NIC_F_VF_MAC = BIT(15),

	NIC_F_RATE_LIMIT = BIT(16),

	NIC_F_RXQ_RECOVERY = BIT(17),

	NIC_F_TX_COMPACT_WQE_OL = BIT(19),

	NIC_F_RX_COMPACT_CQE = BIT(20),

	NIC_F_HTN_CMDQ = BIT(21),

};

drivers/net/ethernet/huawei/hinic3/hinic3_nic_cfg.h

+1 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ u64 hinic3_get_feature_cap(void *hwdev); 
#define HINIC3_SUPPORT_ALLMULTI(hwdev) HINIC3_SUPPORT_FEATURE(hwdev, ALLMULTI)

#define HINIC3_SUPPORT_VF_MAC(hwdev) HINIC3_SUPPORT_FEATURE(hwdev, VF_MAC)

#define HINIC3_SUPPORT_RATE_LIMIT(hwdev) HINIC3_SUPPORT_FEATURE(hwdev, RATE_LIMIT)

#define HINIC3_SUPPORT_TX_COMPACT_WQE_OL(hwdev) HINIC3_SUPPORT_FEATURE(hwdev, TX_COMPACT_WQE_OL)

#define HINIC3_SUPPORT_RX_COMPACT_CQE(hwdev) HINIC3_SUPPORT_FEATURE(hwdev, RX_COMPACT_CQE)



#define HINIC3_SUPPORT_RXQ_RECOVERY(hwdev) HINIC3_SUPPORT_FEATURE(hwdev, RXQ_RECOVERY)

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h

+2 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ struct hinic3_nic_db { 
};



struct hinic3_tx_rx_ops {

	void (*tx_set_wqebb_cnt)(void *wqe_combo, u32 offload, u16 num_sge);

	void (*tx_set_wqe_task)(void *wqe_combo, void *offload_info);

	void (*rx_get_cqe_info)(void *rx_cqe, void *cqe_info);

	bool (*rx_cqe_done)(void *rxq, void **rx_cqe);

};

drivers/net/ethernet/huawei/hinic3/hinic3_nic_qp.h

+89 −29
Original line number Diff line number Diff line
@@ -284,9 +284,13 @@ struct hinic3_sq_wqe_combo { 
	struct hinic3_sq_task *task;

	struct hinic3_sq_bufdesc *bds_head;

	struct hinic3_sq_bufdesc *bds_sec2;



	u16 first_bds_num;

	u32 wqe_type;

	u32 task_type;



	u16 wqebb_cnt;

	u8 rsvd[2];

};



/* ************* SQ_CTRL ************** */
@@ -300,10 +304,37 @@ enum sq_wqe_ec_type { 
};



enum sq_wqe_tasksect_len_type {

	SQ_WQE_TASKSECT_46BITS = 0,

	SQ_WQE_TASKSECT_4BYTES = 0,

	SQ_WQE_TASKSECT_16BYTES = 1,

};



struct hinic3_offload_info {

	u8 encapsulation;

	u8 esp_next_proto;

	u8 inner_l4_en;

	u8 inner_l3_en;

	u8 out_l4_en;

	u8 out_l3_en;

	u8 ipsec_offload;

	u8 pkt_1588;

	u8 vlan_sel;

	u8 vlan_valid;

	u16 vlan1_tag;

	u32 ip_identify;

};



struct hinic3_queue_info {

	u8 pri;

	u8 uc;

	u8 sctp;

	u8 udp_dp_en;

	u8 tso;

	u8 ufo;

	u8 payload_offset;

	u8 pkt_type;

	u16 mss;

};



#define SQ_CTRL_BD0_LEN_SHIFT 0

#define SQ_CTRL_RSVD_SHIFT 18

#define SQ_CTRL_BUFDESC_NUM_SHIFT 19
@@ -335,7 +366,7 @@ enum sq_wqe_tasksect_len_type { 
#define SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT 2

#define SQ_CTRL_QUEUE_INFO_UFO_SHIFT 10

#define SQ_CTRL_QUEUE_INFO_TSO_SHIFT 11

#define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT 12

#define SQ_CTRL_QUEUE_INFO_UDP_DP_EN_SHIFT 12

#define SQ_CTRL_QUEUE_INFO_MSS_SHIFT 13

#define SQ_CTRL_QUEUE_INFO_SCTP_SHIFT 27

#define SQ_CTRL_QUEUE_INFO_UC_SHIFT 28
@@ -345,7 +376,7 @@ enum sq_wqe_tasksect_len_type { 
#define SQ_CTRL_QUEUE_INFO_PLDOFF_MASK 0xFFU

#define SQ_CTRL_QUEUE_INFO_UFO_MASK 0x1U

#define SQ_CTRL_QUEUE_INFO_TSO_MASK 0x1U

#define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK 0x1U

#define SQ_CTRL_QUEUE_INFO_UDP_DP_EN_MASK 0x1U

#define SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFFU

#define SQ_CTRL_QUEUE_INFO_SCTP_MASK 0x1U

#define SQ_CTRL_QUEUE_INFO_UC_MASK 0x1U
@@ -363,6 +394,61 @@ enum sq_wqe_tasksect_len_type { 
	((val) & (~(SQ_CTRL_QUEUE_INFO_##member##_MASK << \

		    SQ_CTRL_QUEUE_INFO_##member##_SHIFT)))



#define SQ_CTRL_15BIT_QUEUE_INFO_PKT_TYPE_SHIFT 14

#define SQ_CTRL_15BIT_QUEUE_INFO_PLDOFF_SHIFT 16

#define SQ_CTRL_15BIT_QUEUE_INFO_UFO_SHIFT 24

#define SQ_CTRL_15BIT_QUEUE_INFO_TSO_SHIFT 25

#define SQ_CTRL_15BIT_QUEUE_INFO_UDP_DP_EN_SHIFT 26

#define SQ_CTRL_15BIT_QUEUE_INFO_SCTP_SHIFT 27



#define SQ_CTRL_15BIT_QUEUE_INFO_PKT_TYPE_MASK 0x3U

#define SQ_CTRL_15BIT_QUEUE_INFO_PLDOFF_MASK 0xFFU

#define SQ_CTRL_15BIT_QUEUE_INFO_UFO_MASK 0x1U

#define SQ_CTRL_15BIT_QUEUE_INFO_TSO_MASK 0x1U

#define SQ_CTRL_15BIT_QUEUE_INFO_UDP_DP_EN_MASK 0x1U

#define SQ_CTRL_15BIT_QUEUE_INFO_SCTP_MASK 0x1U



#define SQ_CTRL_15BIT_QUEUE_INFO_SET(val, member) \

	(((u32)(val) & SQ_CTRL_15BIT_QUEUE_INFO_##member##_MASK) << \

	 SQ_CTRL_15BIT_QUEUE_INFO_##member##_SHIFT)



#define SQ_CTRL_15BIT_QUEUE_INFO_GET(val, member) \

	(((val) >> SQ_CTRL_15BIT_QUEUE_INFO_##member##_SHIFT) & \

	 SQ_CTRL_15BIT_QUEUE_INFO_##member##_MASK)



#define SQ_CTRL_15BIT_QUEUE_INFO_CLEAR(val, member) \

	((val) & (~(SQ_CTRL_15BIT_QUEUE_INFO_##member##_MASK << \

		    SQ_CTRL_15BIT_QUEUE_INFO_##member##_SHIFT)))



#define	SQ_TASK_INFO_PKT_1588_SHIFT         31

#define	SQ_TASK_INFO_IPSEC_PROTO_SHIFT		30

#define	SQ_TASK_INFO_OUT_L3_EN_SHIFT        28

#define	SQ_TASK_INFO_OUT_L4_EN_SHIFT        27

#define	SQ_TASK_INFO_INNER_L3_EN_SHIFT		25

#define	SQ_TASK_INFO_INNER_L4_EN_SHIFT		24

#define	SQ_TASK_INFO_ESP_NEXT_PROTO_SHIFT	22

#define	SQ_TASK_INFO_VLAN_VALID_SHIFT		19

#define	SQ_TASK_INFO_VLAN_SEL_SHIFT         16

#define	SQ_TASK_INFO_VLAN_TAG_SHIFT         0



#define	SQ_TASK_INFO_PKT_1588_MASK          0x1U

#define	SQ_TASK_INFO_IPSEC_PROTO_MASK		0x1U

#define	SQ_TASK_INFO_OUT_L3_EN_MASK         0x1U

#define	SQ_TASK_INFO_OUT_L4_EN_MASK         0x1U

#define	SQ_TASK_INFO_INNER_L3_EN_MASK		0x1U

#define	SQ_TASK_INFO_INNER_L4_EN_MASK		0x1U

#define	SQ_TASK_INFO_ESP_NEXT_PROTO_MASK	0x3U

#define	SQ_TASK_INFO_VLAN_VALID_MASK		0x1U

#define	SQ_TASK_INFO_VLAN_SEL_MASK          0x7U

#define	SQ_TASK_INFO_VLAN_TAG_MASK          0xFFFFU



#define SQ_TASK_INFO_SET(val, member)			\

		(((u32)(val) & SQ_TASK_INFO_##member##_MASK) <<	\

		SQ_TASK_INFO_##member##_SHIFT)

#define SQ_TASK_INFO_GET(val, member)			\

		(((val) >> SQ_TASK_INFO_##member##_SHIFT) & \

		SQ_TASK_INFO_##member##_MASK)



#define SQ_TASK_INFO0_TUNNEL_FLAG_SHIFT 19

#define SQ_TASK_INFO0_ESP_NEXT_PROTO_SHIFT 22

#define SQ_TASK_INFO0_INNER_L4_EN_SHIFT 24
@@ -419,30 +505,4 @@ enum sq_wqe_tasksect_len_type { 
#define LLT_STATIC_DEF_SAVED

#endif



static inline u32 hinic3_get_pkt_len_for_super_cqe(const struct hinic3_rq_cqe *cqe,

						   bool last)

{

	u32 pkt_len = hinic3_hw_cpu32(cqe->pkt_info);



	if (!last)

		return RQ_CQE_PKT_LEN_GET(pkt_len, FIRST_LEN);

	else

		return RQ_CQE_PKT_LEN_GET(pkt_len, LAST_LEN);

}



/* *

 * hinic3_set_vlan_tx_offload - set vlan offload info

 * @task: wqe task section

 * @vlan_tag: vlan tag

 * @vlan_type: 0--select TPID0 in IPSU, 1--select TPID0 in IPSU

 * 2--select TPID2 in IPSU, 3--select TPID3 in IPSU, 4--select TPID4 in IPSU

 */

static inline void hinic3_set_vlan_tx_offload(struct hinic3_sq_task *task,

					      u16 vlan_tag, u8 vlan_type)

{

	task->vlan_offload = SQ_TASK_INFO3_SET(vlan_tag, VLAN_TAG) |

			     SQ_TASK_INFO3_SET(vlan_type, VLAN_TYPE) |

			     SQ_TASK_INFO3_SET(1U, VLAN_TAG_VALID);

}



#endif