Commit 74d5b415 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v6.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control fixes from Linus Walleij:

 - Fix typos in UART1 and MMC in the Ingenic driver

 - A really well researched glitch bug fix to the Qualcomm driver that
   was tracked down and fixed by Dough Anderson from Chromium. Hats off
   for this one!

 - Revert two patches on the Xilinx ZynqMP driver: this needs a proper
   solution making use of firmware version information to adapt to
   different firmware releases

 - Fix interrupt triggers in the Ocelot driver

* tag 'pinctrl-v6.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: ocelot: Fix incorrect trigger of the interrupt.
  Revert "dt-bindings: pinctrl-zynqmp: Add output-enable configuration"
  Revert "pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high-impedance"
  pinctrl: qcom: Avoid glitching lines when we first mux to output
  pinctrl: Ingenic: JZ4755 bug fixes
parents 247f34f7 e9945b26

Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml

+0 −4
Original line number Diff line number Diff line
@@ -274,10 +274,6 @@ patternProperties: 
          slew-rate:

            enum: [0, 1]



          output-enable:

            description:

              This will internally disable the tri-state for MIO pins.



          drive-strength:

            description:

              Selects the drive strength for MIO pins, in mA.

drivers/pinctrl/pinctrl-ingenic.c

+2 −2
Original line number Diff line number Diff line
@@ -667,7 +667,7 @@ static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, }; 
static const struct group_desc jz4755_groups[] = {

	INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),

	INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),

	INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0),

	INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),

	INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),

	INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),

	INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
@@ -721,7 +721,7 @@ static const char *jz4755_ssi_groups[] = { 
	"ssi-ce1-b", "ssi-ce1-f",

};

static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };

static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };

static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };

static const char *jz4755_i2c_groups[] = { "i2c-data", };

static const char *jz4755_cim_groups[] = { "cim-data", };

static const char *jz4755_lcd_groups[] = {

drivers/pinctrl/pinctrl-ocelot.c

+13 −4
Original line number Diff line number Diff line
@@ -1864,19 +1864,28 @@ static void ocelot_irq_unmask_level(struct irq_data *data) 
	if (val & bit)

		ack = true;



	/* Try to clear any rising edges */

	if (!active && ack)

		regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),

				  bit, bit);



	/* Enable the interrupt now */

	gpiochip_enable_irq(chip, gpio);

	regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),

			   bit, bit);



	/*

	 * In case the interrupt line is still active and the interrupt

	 * controller has not seen any changes in the interrupt line, then it

	 * means that there happen another interrupt while the line was active.

	 * In case the interrupt line is still active then it means that

	 * there happen another interrupt while the line was active.

	 * So we missed that one, so we need to kick the interrupt again

	 * handler.

	 */

	if (active && !ack) {

	regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);

	if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||

	      (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH))

		active = true;



	if (active) {

		struct ocelot_irq_work *work;



		work = kmalloc(sizeof(*work), GFP_ATOMIC);

drivers/pinctrl/pinctrl-zynqmp.c

+0 −9
Original line number Diff line number Diff line
@@ -412,10 +412,6 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, 


			break;

		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:

			param = PM_PINCTRL_CONFIG_TRI_STATE;

			arg = PM_PINCTRL_TRI_STATE_ENABLE;

			ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);

			break;

		case PIN_CONFIG_MODE_LOW_POWER:

			/*

			 * These cases are mentioned in dts but configurable
@@ -424,11 +420,6 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, 
			 */

			ret = 0;

			break;

		case PIN_CONFIG_OUTPUT_ENABLE:

			param = PM_PINCTRL_CONFIG_TRI_STATE;

			arg = PM_PINCTRL_TRI_STATE_DISABLE;

			ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);

			break;

		default:

			dev_warn(pctldev->dev,

				 "unsupported configuration parameter '%u'\n",

drivers/pinctrl/qcom/pinctrl-msm.c

+21 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ 
 *                  detection.

 * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller

 * @disabled_for_mux: These IRQs were disabled because we muxed away.

 * @ever_gpio:      This bit is set the first time we mux a pin to gpio_func.

 * @soc:            Reference to soc_data of platform specific data.

 * @regs:           Base addresses for the TLMM tiles.

 * @phys_base:      Physical base address
@@ -72,6 +73,7 @@ struct msm_pinctrl { 
	DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);

	DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);

	DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO);

	DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);



	const struct msm_pinctrl_soc_data *soc;

	void __iomem *regs[MAX_NR_TILES];
@@ -218,6 +220,25 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 


	val = msm_readl_ctl(pctrl, g);



	/*

	 * If this is the first time muxing to GPIO and the direction is

	 * output, make sure that we're not going to be glitching the pin

	 * by reading the current state of the pin and setting it as the

	 * output.

	 */

	if (i == gpio_func && (val & BIT(g->oe_bit)) &&

	    !test_and_set_bit(group, pctrl->ever_gpio)) {

		u32 io_val = msm_readl_io(pctrl, g);



		if (io_val & BIT(g->in_bit)) {

			if (!(io_val & BIT(g->out_bit)))

				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);

		} else {

			if (io_val & BIT(g->out_bit))

				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);

		}

	}



	if (egpio_func && i == egpio_func) {

		if (val & BIT(g->egpio_present))

			val &= ~BIT(g->egpio_enable);