Commit 746ce767 authored by Dave Thaler's avatar Dave Thaler Committed by Alexei Starovoitov
Browse files

bpf, docs: Add explanation of endianness 



Document the discussion from the email thread on the IETF bpf list,
where it was explained that the raw format varies by endianness
of the processor.

Signed-off-by: default avatarDave Thaler <dthaler@microsoft.com>
Acked-by: default avatarDavid Vernet <void@manifault.com>
Link: https://lore.kernel.org/r/20230220223742.1347-1-dthaler1968@googlemail.com


Signed-off-by: default avatarAlexei Starovoitov <ast@kernel.org>
parent 9fa02892

Documentation/bpf/instruction-set.rst

+14 −2
Original line number Diff line number Diff line
@@ -38,8 +38,9 @@ eBPF has two instruction encodings: 
* the wide instruction encoding, which appends a second 64-bit immediate (i.e.,

  constant) value after the basic instruction for a total of 128 bits.



The basic instruction encoding is as follows, where MSB and LSB mean the most significant

bits and least significant bits, respectively:

The basic instruction encoding looks as follows for a little-endian processor,

where MSB and LSB mean the most significant bits and least significant bits,

respectively:



=============  =======  =======  =======  ============

32 bits (MSB)  16 bits  4 bits   4 bits   8 bits (LSB)
@@ -63,6 +64,17 @@ imm offset src_reg dst_reg opcode 
**opcode**

  operation to perform



and as follows for a big-endian processor:



=============  =======  =======  =======  ============

32 bits (MSB)  16 bits  4 bits   4 bits   8 bits (LSB)

=============  =======  =======  =======  ============

imm            offset   dst_reg  src_reg  opcode

=============  =======  =======  =======  ============



Multi-byte fields ('imm' and 'offset') are similarly stored in

the byte order of the processor.



Note that most instructions do not use all of the fields.

Unused fields shall be cleared to zero.