Commit 74273035 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
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dt-bindings: pinctrl: renesas: Document RZ/G2UL pinctrl 



Document Renesas RZ/G2UL pinctrl bindings. RZ/G2UL GPIO block is
almost identical to RZ/G2L and has lesser pins compared to RZ/G2L.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220315152717.20045-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 29af6344

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+3 −2
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ maintainers: 
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO

  controller.

  The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and

  GPIO controller.

  Pin multiplexing and GPIO configuration is performed on a per-pin basis.

  Each port features up to 8 pins, each of them configurable for GPIO function

  (port mode) or in alternate function mode.
@@ -23,6 +23,7 @@ properties: 
    oneOf:

      - items:

          - enum:

              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}

              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}



      - items: