Commit 74081de4 authored by Vidya Sagar's avatar Vidya Sagar Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Add support to program ATU for >4GB memory 

Add support to program the ATU to enable translations for >4GB sizes of
the prefetchable memory apertures.

Link: https://lore.kernel.org/r/20201118144626.32189-3-vidyas@nvidia.com


Tested-by: default avatarThierry Reding <treding@nvidia.com>
Tested-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarJingoo <jingoohan1@gmail.com>
parent fede8526

drivers/pci/controller/dwc/pcie-designware.c

+7 −5
Original line number Diff line number Diff line
@@ -228,7 +228,7 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg, 
static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,

					     int index, int type,

					     u64 cpu_addr, u64 pci_addr,

					     u32 size)

					     u64 size)

{

	u32 retries, val;

	u64 limit_addr = cpu_addr + size - 1;
@@ -245,8 +245,10 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, 
				 lower_32_bits(pci_addr));

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,

				 upper_32_bits(pci_addr));

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,

				 type | PCIE_ATU_FUNC_NUM(func_no));

	val = type | PCIE_ATU_FUNC_NUM(func_no);

	val = upper_32_bits(size - 1) ?

		val | PCIE_ATU_INCREASE_REGION_SIZE : val;

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val);

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,

				 PCIE_ATU_ENABLE);
@@ -267,7 +269,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, 


static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,

					int index, int type, u64 cpu_addr,

					u64 pci_addr, u32 size)

					u64 pci_addr, u64 size)

{

	u32 retries, val;
@@ -311,7 +313,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, 
}



void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,

			       u64 cpu_addr, u64 pci_addr, u32 size)

			       u64 cpu_addr, u64 pci_addr, u64 size)

{

	__dw_pcie_prog_outbound_atu(pci, 0, index, type,

				    cpu_addr, pci_addr, size);

drivers/pci/controller/dwc/pcie-designware.h

+2 −1
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ 
#define PCIE_ATU_REGION_INBOUND		BIT(31)

#define PCIE_ATU_REGION_OUTBOUND	0

#define PCIE_ATU_CR1			0x904

#define PCIE_ATU_INCREASE_REGION_SIZE	BIT(13)

#define PCIE_ATU_TYPE_MEM		0x0

#define PCIE_ATU_TYPE_IO		0x2

#define PCIE_ATU_TYPE_CFG0		0x4
@@ -293,7 +294,7 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci); 
int dw_pcie_wait_for_link(struct dw_pcie *pci);

void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,

			       int type, u64 cpu_addr, u64 pci_addr,

			       u32 size);

			       u64 size);

void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,

				  int type, u64 cpu_addr, u64 pci_addr,

				  u32 size);