Unverified Commit 73ff4d18 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'sunxi-dt-for-5.19-1' of... 

Merge tag 'sunxi-dt-for-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

- F1C100 improvements (SPI, MMC, timer, cpu, watchdog)
- SPI flash node for licheepi-nano
- enabled analogue audio on olinuxino-a64
- GPIO port regulators on teres-i

* tag 'sunxi-dt-for-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: teres-i: Add GPIO port regulators
  arm64: dts: allwinner: a64: olinuxino: Enable audio
  ARM: dts: suniv: licheepi-nano: add SPI flash
  ARM: dts: suniv: F1C100: add SPI support
  dt-bindings: spi: sunxi: document F1C100 controllers
  ARM: dts: suniv: licheepi-nano: add microSD card
  ARM: dts: suniv: F1C100: add MMC controllers
  ARM: dts: suniv: F1C100: fix timer node
  ARM: dts: suniv: F1C100: fix CPU node
  ARM: dts: suniv: F1C100: add clock and reset macros
  dt-bindings: arm: sunxi: document LicheePi Nano name
  ARM: dts: suniv: F1C100: fix watchdog compatible
  dt-bindings: watchdog: sunxi: clarify clock support
  dt-bindings: watchdog: sunxi: fix F1C100s compatible

Link: https://lore.kernel.org/r/YnVUmSLE1MZFkApt@kista.localdomain


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 1bc44c1e 50612cf9

Documentation/devicetree/bindings/arm/sunxi.yaml

+5 −0
Original line number Diff line number Diff line
@@ -391,6 +391,11 @@ properties: 
          - const: libretech,all-h5-cc-h5

          - const: allwinner,sun50i-h5



      - description: Lichee Pi Nano

        items:

          - const: licheepi,licheepi-nano

          - const: allwinner,suniv-f1c100s



      - description: Lichee Pi One

        items:

          - const: licheepi,licheepi-one

Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ properties: 
              - allwinner,sun8i-r40-spi

              - allwinner,sun50i-h6-spi

              - allwinner,sun50i-h616-spi

              - allwinner,suniv-f1c100s-spi

          - const: allwinner,sun8i-h3-spi



  reg:

Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml

+9 −15
Original line number Diff line number Diff line
@@ -26,10 +26,8 @@ properties: 
              - allwinner,sun50i-h616-wdt

              - allwinner,sun50i-r329-wdt

              - allwinner,sun50i-r329-wdt-reset

              - allwinner,suniv-f1c100s-wdt

          - const: allwinner,sun6i-a31-wdt

      - items:

          - const: allwinner,suniv-f1c100s-wdt

          - const: allwinner,sun4i-a10-wdt

      - const: allwinner,sun20i-d1-wdt

      - items:

          - const: allwinner,sun20i-d1-wdt-reset
@@ -41,14 +39,8 @@ properties: 
  clocks:

    minItems: 1

    items:

      - description: High-frequency oscillator input, divided internally

      - description: Low-frequency oscillator input, only found on some variants



  clock-names:

    minItems: 1

    items:

      - const: hosc

      - const: losc

      - description: 32 KHz input clock

      - description: secondary clock source



  interrupts:

    maxItems: 1
@@ -73,9 +65,14 @@ then: 
  properties:

    clocks:

      minItems: 2

      items:

        - description: High-frequency oscillator input, divided internally

        - description: Low-frequency oscillator input



    clock-names:

      minItems: 2

      items:

        - const: hosc

        - const: losc



  required:

    - clock-names
@@ -85,9 +82,6 @@ else: 
    clocks:

      maxItems: 1



    clock-names:

      maxItems: 1



unevaluatedProperties: false



examples:

arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts

+31 −0
Original line number Diff line number Diff line
@@ -11,12 +11,43 @@ 
	compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";



	aliases {

		mmc0 = &mmc0;

		serial0 = &uart0;

		spi0 = &spi0;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	reg_vcc3v3: vcc3v3 {

		compatible = "regulator-fixed";

		regulator-name = "vcc3v3";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

	};

};



&mmc0 {

	broken-cd;

	bus-width = <4>;

	disable-wp;

	status = "okay";

	vmmc-supply = <&reg_vcc3v3>;

};



&spi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi0_pc_pins>;

	status = "okay";



	flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "winbond,w25q128", "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <40000000>;

	};

};



&uart0 {

arch/arm/boot/dts/suniv-f1c100s.dtsi

+94 −10
Original line number Diff line number Diff line
@@ -4,6 +4,9 @@ 
 * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>

 */



#include <dt-bindings/clock/suniv-ccu-f1c100s.h>

#include <dt-bindings/reset/suniv-ccu-f1c100s.h>



/ {

	#address-cells = <1>;

	#size-cells = <1>;
@@ -26,9 +29,13 @@ 
	};



	cpus {

		cpu {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "arm,arm926ej-s";

			device_type = "cpu";

			reg = <0x0>;

		};

	};
@@ -62,6 +69,70 @@ 
			};

		};



		spi0: spi@1c05000 {

			compatible = "allwinner,suniv-f1c100s-spi",

				     "allwinner,sun8i-h3-spi";

			reg = <0x01c05000 0x1000>;

			interrupts = <10>;

			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;

			clock-names = "ahb", "mod";

			resets = <&ccu RST_BUS_SPI0>;

			status = "disabled";

			num-cs = <1>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi1: spi@1c06000 {

			compatible = "allwinner,suniv-f1c100s-spi",

				     "allwinner,sun8i-h3-spi";

			reg = <0x01c06000 0x1000>;

			interrupts = <11>;

			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;

			clock-names = "ahb", "mod";

			resets = <&ccu RST_BUS_SPI1>;

			status = "disabled";

			num-cs = <1>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		mmc0: mmc@1c0f000 {

			compatible = "allwinner,suniv-f1c100s-mmc",

				     "allwinner,sun7i-a20-mmc";

			reg = <0x01c0f000 0x1000>;

			clocks = <&ccu CLK_BUS_MMC0>,

				 <&ccu CLK_MMC0>,

				 <&ccu CLK_MMC0_OUTPUT>,

				 <&ccu CLK_MMC0_SAMPLE>;

			clock-names = "ahb", "mmc", "output", "sample";

			resets = <&ccu RST_BUS_MMC0>;

			reset-names = "ahb";

			interrupts = <23>;

			pinctrl-names = "default";

			pinctrl-0 = <&mmc0_pins>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		mmc1: mmc@1c10000 {

			compatible = "allwinner,suniv-f1c100s-mmc",

				     "allwinner,sun7i-a20-mmc";

			reg = <0x01c10000 0x1000>;

			clocks = <&ccu CLK_BUS_MMC1>,

				 <&ccu CLK_MMC1>,

				 <&ccu CLK_MMC1_OUTPUT>,

				 <&ccu CLK_MMC1_SAMPLE>;

			clock-names = "ahb", "mmc", "output", "sample";

			resets = <&ccu RST_BUS_MMC1>;

			reset-names = "ahb";

			interrupts = <24>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		ccu: clock@1c20000 {

			compatible = "allwinner,suniv-f1c100s-ccu";

			reg = <0x01c20000 0x400>;
@@ -82,13 +153,24 @@ 
			compatible = "allwinner,suniv-f1c100s-pinctrl";

			reg = <0x01c20800 0x400>;

			interrupts = <38>, <39>, <40>;

			clocks = <&ccu 37>, <&osc24M>, <&osc32k>;

			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			gpio-controller;

			interrupt-controller;

			#interrupt-cells = <3>;

			#gpio-cells = <3>;



			mmc0_pins: mmc0-pins {

				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";

				function = "mmc0";

				drive-strength = <30>;

			};



			spi0_pc_pins: spi0-pc-pins {

				pins = "PC0", "PC1", "PC2", "PC3";

				function = "spi0";

			};



			uart0_pe_pins: uart0-pe-pins {

				pins = "PE0", "PE1";

				function = "uart0";
@@ -98,14 +180,16 @@ 
		timer@1c20c00 {

			compatible = "allwinner,suniv-f1c100s-timer";

			reg = <0x01c20c00 0x90>;

			interrupts = <13>;

			interrupts = <13>, <14>, <15>;

			clocks = <&osc24M>;

		};



		wdt: watchdog@1c20ca0 {

			compatible = "allwinner,suniv-f1c100s-wdt",

				     "allwinner,sun4i-a10-wdt";

				     "allwinner,sun6i-a31-wdt";

			reg = <0x01c20ca0 0x20>;

			interrupts = <16>;

			clocks = <&osc32k>;

		};



		uart0: serial@1c25000 {
@@ -114,8 +198,8 @@ 
			interrupts = <1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu 38>;

			resets = <&ccu 24>;

			clocks = <&ccu CLK_BUS_UART0>;

			resets = <&ccu RST_BUS_UART0>;

			status = "disabled";

		};
@@ -125,8 +209,8 @@ 
			interrupts = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu 39>;

			resets = <&ccu 25>;

			clocks = <&ccu CLK_BUS_UART1>;

			resets = <&ccu RST_BUS_UART1>;

			status = "disabled";

		};
@@ -136,8 +220,8 @@ 
			interrupts = <3>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu 40>;

			resets = <&ccu 26>;

			clocks = <&ccu CLK_BUS_UART2>;

			resets = <&ccu RST_BUS_UART2>;

			status = "disabled";

		};

	};