Commit 73d37247 authored by jason-jh.lin's avatar jason-jh.lin Committed by Chun-Kuang Hu
Browse files

drm/mediatek: Adjust to the alphabetic order for mediatek-drm 



Adjust to the alphabetic order for the define, function, struct
and array in mediatek-drm driver

Signed-off-by: default avatarjason-jh.lin <jason-jh.lin@mediatek.com>
Signed-off-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
parent aa0c3155

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

+59 −62
Original line number Diff line number Diff line
@@ -20,42 +20,40 @@ 
#include "mtk_drm_ddp_comp.h"

#include "mtk_drm_crtc.h"



#define DISP_REG_OD_EN				0x0000

#define DISP_REG_OD_CFG				0x0020

#define DISP_REG_OD_SIZE			0x0030

#define DISP_REG_DITHER_5			0x0114

#define DISP_REG_DITHER_7			0x011c

#define DISP_REG_DITHER_15			0x013c

#define DISP_REG_DITHER_16			0x0140



#define DISP_REG_UFO_START			0x0000



#define DISP_REG_DITHER_EN			0x0000

#define DITHER_EN				BIT(0)

#define DISP_REG_DITHER_CFG			0x0020

#define DITHER_RELAY_MODE			BIT(0)

#define DITHER_ENGINE_EN			BIT(1)

#define DISP_REG_DITHER_SIZE			0x0030



#define OD_RELAYMODE				BIT(0)



#define UFO_BYPASS				BIT(2)



#define DISP_DITHERING				BIT(2)

#define DISP_REG_DITHER_SIZE			0x0030

#define DISP_REG_DITHER_5			0x0114

#define DISP_REG_DITHER_7			0x011c

#define DISP_REG_DITHER_15			0x013c

#define DITHER_LSB_ERR_SHIFT_R(x)		(((x) & 0x7) << 28)

#define DITHER_ADD_LSHIFT_R(x)			(((x) & 0x7) << 20)

#define DITHER_NEW_BIT_MODE			BIT(0)

#define DISP_REG_DITHER_16			0x0140

#define DITHER_LSB_ERR_SHIFT_B(x)		(((x) & 0x7) << 28)

#define DITHER_ADD_LSHIFT_B(x)			(((x) & 0x7) << 20)

#define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)

#define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)



#define DISP_REG_OD_EN				0x0000

#define DISP_REG_OD_CFG				0x0020

#define OD_RELAYMODE				BIT(0)

#define DISP_REG_OD_SIZE			0x0030



#define DISP_REG_POSTMASK_EN			0x0000

#define POSTMASK_EN					BIT(0)

#define DISP_REG_POSTMASK_CFG			0x0020

#define POSTMASK_RELAY_MODE				BIT(0)

#define DISP_REG_POSTMASK_SIZE			0x0030



#define DISP_REG_UFO_START			0x0000

#define UFO_BYPASS				BIT(2)



struct mtk_ddp_comp_dev {

	struct clk *clk;

	void __iomem *regs;
@@ -147,66 +145,58 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, 
	}

}



static void mtk_dither_set(struct device *dev, unsigned int bpc,

		    unsigned int cfg, struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,

			      DISP_DITHERING, cmdq_pkt);

}



static void mtk_od_config(struct device *dev, unsigned int w,

static void mtk_dither_config(struct device *dev, unsigned int w,

			      unsigned int h, unsigned int vrefresh,

			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);

	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);

	mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);

	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);

	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,

		      DISP_REG_DITHER_CFG);

	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,

			      DITHER_ENGINE_EN, cmdq_pkt);

}



static void mtk_od_start(struct device *dev)

static void mtk_dither_start(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel(1, priv->regs + DISP_REG_OD_EN);

	writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);

}



static void mtk_ufoe_start(struct device *dev)

static void mtk_dither_stop(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);

	writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);

}



static void mtk_dither_config(struct device *dev, unsigned int w,

			      unsigned int h, unsigned int vrefresh,

			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

static void mtk_dither_set(struct device *dev, unsigned int bpc,

			   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,

		      DISP_REG_DITHER_SIZE);

	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,

		      DISP_REG_DITHER_CFG);

	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,

			      DITHER_ENGINE_EN, cmdq_pkt);

	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,

			      DISP_DITHERING, cmdq_pkt);

}



static void mtk_dither_start(struct device *dev)

static void mtk_od_config(struct device *dev, unsigned int w,

			  unsigned int h, unsigned int vrefresh,

			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);

	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);

	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);

	mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);

}



static void mtk_dither_stop(struct device *dev)

static void mtk_od_start(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);

	writel(1, priv->regs + DISP_REG_OD_EN);

}



static void mtk_postmask_config(struct device *dev, unsigned int w,
@@ -235,6 +225,13 @@ static void mtk_postmask_stop(struct device *dev) 
	writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);

}



static void mtk_ufoe_start(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);

}



static const struct mtk_ddp_comp_funcs ddp_aal = {

	.clk_enable = mtk_aal_clk_enable,

	.clk_disable = mtk_aal_clk_disable,
@@ -337,23 +334,23 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = { 
};



static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {

	[MTK_DISP_OVL] = "ovl",

	[MTK_DISP_OVL_2L] = "ovl-2l",

	[MTK_DISP_RDMA] = "rdma",

	[MTK_DISP_WDMA] = "wdma",

	[MTK_DISP_COLOR] = "color",

	[MTK_DISP_CCORR] = "ccorr",

	[MTK_DISP_AAL] = "aal",

	[MTK_DISP_GAMMA] = "gamma",

	[MTK_DISP_BLS] = "bls",

	[MTK_DISP_CCORR] = "ccorr",

	[MTK_DISP_COLOR] = "color",

	[MTK_DISP_DITHER] = "dither",

	[MTK_DISP_UFOE] = "ufoe",

	[MTK_DSI] = "dsi",

	[MTK_DPI] = "dpi",

	[MTK_DISP_PWM] = "pwm",

	[MTK_DISP_GAMMA] = "gamma",

	[MTK_DISP_MUTEX] = "mutex",

	[MTK_DISP_OD] = "od",

	[MTK_DISP_BLS] = "bls",

	[MTK_DISP_OVL] = "ovl",

	[MTK_DISP_OVL_2L] = "ovl-2l",

	[MTK_DISP_POSTMASK] = "postmask",

	[MTK_DISP_PWM] = "pwm",

	[MTK_DISP_RDMA] = "rdma",

	[MTK_DISP_UFOE] = "ufoe",

	[MTK_DISP_WDMA] = "wdma",

	[MTK_DPI] = "dpi",

	[MTK_DSI] = "dsi",

};



struct mtk_ddp_comp_match {
@@ -511,12 +508,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, 
	    type == MTK_DISP_CCORR ||

	    type == MTK_DISP_COLOR ||

	    type == MTK_DISP_GAMMA ||

	    type == MTK_DPI ||

	    type == MTK_DSI ||

	    type == MTK_DISP_OVL ||

	    type == MTK_DISP_OVL_2L ||

	    type == MTK_DISP_PWM ||

	    type == MTK_DISP_RDMA)

	    type == MTK_DISP_RDMA ||

	    type == MTK_DPI ||

	    type == MTK_DSI)

		return 0;



	priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h

+12 −12
Original line number Diff line number Diff line
@@ -18,23 +18,23 @@ struct mtk_plane_state; 
struct drm_crtc_state;



enum mtk_ddp_comp_type {

	MTK_DISP_OVL,

	MTK_DISP_OVL_2L,

	MTK_DISP_RDMA,

	MTK_DISP_WDMA,

	MTK_DISP_COLOR,

	MTK_DISP_AAL,

	MTK_DISP_BLS,

	MTK_DISP_CCORR,

	MTK_DISP_COLOR,

	MTK_DISP_DITHER,

	MTK_DISP_AAL,

	MTK_DISP_GAMMA,

	MTK_DISP_UFOE,

	MTK_DSI,

	MTK_DPI,

	MTK_DISP_POSTMASK,

	MTK_DISP_PWM,

	MTK_DISP_MUTEX,

	MTK_DISP_OD,

	MTK_DISP_BLS,

	MTK_DISP_OVL,

	MTK_DISP_OVL_2L,

	MTK_DISP_POSTMASK,

	MTK_DISP_PWM,

	MTK_DISP_RDMA,

	MTK_DISP_UFOE,

	MTK_DISP_WDMA,

	MTK_DPI,

	MTK_DSI,

	MTK_DDP_COMP_TYPE_MAX,

};

drivers/gpu/drm/mediatek/mtk_drm_drv.c

+60 −60
Original line number Diff line number Diff line
@@ -423,32 +423,14 @@ static const struct component_master_ops mtk_drm_ops = { 
};



static const struct of_device_id mtk_ddp_comp_dt_ids[] = {

	{ .compatible = "mediatek,mt2701-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8167-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8173-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8183-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8183-disp-ovl-2l",

	  .data = (void *)MTK_DISP_OVL_2L },

	{ .compatible = "mediatek,mt8192-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8192-disp-ovl-2l",

	  .data = (void *)MTK_DISP_OVL_2L },

	{ .compatible = "mediatek,mt2701-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8167-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8173-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8183-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8192-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8173-disp-wdma",

	  .data = (void *)MTK_DISP_WDMA },

	{ .compatible = "mediatek,mt8167-disp-aal",

	  .data = (void *)MTK_DISP_AAL},

	{ .compatible = "mediatek,mt8173-disp-aal",

	  .data = (void *)MTK_DISP_AAL},

	{ .compatible = "mediatek,mt8183-disp-aal",

	  .data = (void *)MTK_DISP_AAL},

	{ .compatible = "mediatek,mt8192-disp-aal",

	  .data = (void *)MTK_DISP_AAL},

	{ .compatible = "mediatek,mt8167-disp-ccorr",

	  .data = (void *)MTK_DISP_CCORR },

	{ .compatible = "mediatek,mt8183-disp-ccorr",
@@ -461,40 +443,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 
	  .data = (void *)MTK_DISP_COLOR },

	{ .compatible = "mediatek,mt8173-disp-color",

	  .data = (void *)MTK_DISP_COLOR },

	{ .compatible = "mediatek,mt8167-disp-aal",

	  .data = (void *)MTK_DISP_AAL},

	{ .compatible = "mediatek,mt8173-disp-aal",

	  .data = (void *)MTK_DISP_AAL},

	{ .compatible = "mediatek,mt8183-disp-aal",

	  .data = (void *)MTK_DISP_AAL},

	{ .compatible = "mediatek,mt8192-disp-aal",

	  .data = (void *)MTK_DISP_AAL},

	{ .compatible = "mediatek,mt8167-disp-dither",

	  .data = (void *)MTK_DISP_DITHER },

	{ .compatible = "mediatek,mt8183-disp-dither",

	  .data = (void *)MTK_DISP_DITHER },

	{ .compatible = "mediatek,mt8167-disp-gamma",

	  .data = (void *)MTK_DISP_GAMMA, },

	{ .compatible = "mediatek,mt8173-disp-gamma",

	  .data = (void *)MTK_DISP_GAMMA, },

	{ .compatible = "mediatek,mt8183-disp-gamma",

	  .data = (void *)MTK_DISP_GAMMA, },

	{ .compatible = "mediatek,mt8167-disp-dither",

	  .data = (void *)MTK_DISP_DITHER },

	{ .compatible = "mediatek,mt8183-disp-dither",

	  .data = (void *)MTK_DISP_DITHER },

	{ .compatible = "mediatek,mt8173-disp-ufoe",

	  .data = (void *)MTK_DISP_UFOE },

	{ .compatible = "mediatek,mt2701-dsi",

	  .data = (void *)MTK_DSI },

	{ .compatible = "mediatek,mt8167-dsi",

	  .data = (void *)MTK_DSI },

	{ .compatible = "mediatek,mt8173-dsi",

	  .data = (void *)MTK_DSI },

	{ .compatible = "mediatek,mt8183-dsi",

	  .data = (void *)MTK_DSI },

	{ .compatible = "mediatek,mt2701-dpi",

	  .data = (void *)MTK_DPI },

	{ .compatible = "mediatek,mt8173-dpi",

	  .data = (void *)MTK_DPI },

	{ .compatible = "mediatek,mt8183-dpi",

	  .data = (void *)MTK_DPI },

	{ .compatible = "mediatek,mt2701-disp-mutex",

	  .data = (void *)MTK_DISP_MUTEX },

	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -507,16 +465,58 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 
	  .data = (void *)MTK_DISP_MUTEX },

	{ .compatible = "mediatek,mt8192-disp-mutex",

	  .data = (void *)MTK_DISP_MUTEX },

	{ .compatible = "mediatek,mt8173-disp-od",

	  .data = (void *)MTK_DISP_OD },

	{ .compatible = "mediatek,mt2701-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8167-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8173-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8183-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8192-disp-ovl",

	  .data = (void *)MTK_DISP_OVL },

	{ .compatible = "mediatek,mt8183-disp-ovl-2l",

	  .data = (void *)MTK_DISP_OVL_2L },

	{ .compatible = "mediatek,mt8192-disp-ovl-2l",

	  .data = (void *)MTK_DISP_OVL_2L },

	{ .compatible = "mediatek,mt8192-disp-postmask",

	  .data = (void *)MTK_DISP_POSTMASK },

	{ .compatible = "mediatek,mt2701-disp-pwm",

	  .data = (void *)MTK_DISP_BLS },

	{ .compatible = "mediatek,mt8167-disp-pwm",

	  .data = (void *)MTK_DISP_PWM },

	{ .compatible = "mediatek,mt8173-disp-pwm",

	  .data = (void *)MTK_DISP_PWM },

	{ .compatible = "mediatek,mt8173-disp-od",

	  .data = (void *)MTK_DISP_OD },

	{ .compatible = "mediatek,mt8192-disp-postmask",

	  .data = (void *)MTK_DISP_POSTMASK },

	{ .compatible = "mediatek,mt2701-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8167-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8173-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8183-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8192-disp-rdma",

	  .data = (void *)MTK_DISP_RDMA },

	{ .compatible = "mediatek,mt8173-disp-ufoe",

	  .data = (void *)MTK_DISP_UFOE },

	{ .compatible = "mediatek,mt8173-disp-wdma",

	  .data = (void *)MTK_DISP_WDMA },

	{ .compatible = "mediatek,mt2701-dpi",

	  .data = (void *)MTK_DPI },

	{ .compatible = "mediatek,mt8167-dsi",

	  .data = (void *)MTK_DSI },

	{ .compatible = "mediatek,mt8173-dpi",

	  .data = (void *)MTK_DPI },

	{ .compatible = "mediatek,mt8183-dpi",

	  .data = (void *)MTK_DPI },

	{ .compatible = "mediatek,mt2701-dsi",

	  .data = (void *)MTK_DSI },

	{ .compatible = "mediatek,mt8173-dsi",

	  .data = (void *)MTK_DSI },

	{ .compatible = "mediatek,mt8183-dsi",

	  .data = (void *)MTK_DSI },

	{ }

};
@@ -610,8 +610,8 @@ static int mtk_drm_probe(struct platform_device *pdev) 
		    comp_type == MTK_DISP_OVL ||

		    comp_type == MTK_DISP_OVL_2L ||

		    comp_type == MTK_DISP_RDMA ||

		    comp_type == MTK_DSI ||

		    comp_type == MTK_DPI) {

		    comp_type == MTK_DPI ||

		    comp_type == MTK_DSI) {

			dev_info(dev, "Adding component match for %pOF\n",

				 node);

			drm_of_component_match_add(dev, &match, compare_of,