Commit 73d04ca5 authored by Linus Walleij's avatar Linus Walleij
Browse files

ARM: ixp4xx: Delete Intel reference design boardfiles 



These boards are replaced with the corresponding device trees.

Cc: Deepak Saxena <dsaxena@plexity.net>
Cc: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent b00ced38

arch/arm/mach-ixp4xx/Kconfig

+0 −37
Original line number Diff line number Diff line
@@ -33,14 +33,6 @@ config MACH_GATEWAY7001 
	  7001 Access Point. For more information on this platform,

	  see http://openwrt.org



config ARCH_IXDP425

	bool "IXDP425"

	depends on IXP4XX_PCI_LEGACY

	help

	  Say 'Y' here if you want your kernel to support Intel's 

	  IXDP425 Development Platform (Also known as Richfield).  

	  For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.



config MACH_IXDPG425

	bool "IXDPG425"

	depends on IXP4XX_PCI_LEGACY
@@ -49,36 +41,12 @@ config MACH_IXDPG425 
	  IXDPG425 Development Platform (Also known as Montajade).

	  For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.



config MACH_IXDP465

	bool "IXDP465"

	help

	  Say 'Y' here if you want your kernel to support Intel's

	  IXDP465 Development Platform (Also known as BMP).

	  For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.



config MACH_GORAMO_MLR

	bool "GORAMO Multi Link Router"

	help

	  Say 'Y' here if you want your kernel to support GORAMO

	  MultiLink router.



config MACH_KIXRP435

	bool "KIXRP435"

	help

	  Say 'Y' here if you want your kernel to support Intel's

	  KIXRP435 Reference Platform.

	  For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>.



#

# IXCDP1100 is the exact same HW as IXDP425, but with a different machine 

# number from the bootloader due to marketing monkeys, so we just enable it 

# by default if IXDP425 is enabled.

#

config ARCH_IXCDP1100

	bool 

	depends on ARCH_IXDP425

	default y



config ARCH_PRPMC1100

	bool "PrPMC1100"

	help
@@ -86,11 +54,6 @@ config ARCH_PRPMC1100 
	  PrPCM1100 Processor Mezanine Module. For more information on

	  this platform, see <file:Documentation/arm/ixp4xx.rst>.



config	ARCH_IXDP4XX

	bool

	depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435

	default y



config MACH_FSG

	bool

	prompt "Freecom FSG-3"

arch/arm/mach-ixp4xx/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ obj-pci-n := 
# Device tree platform

obj-pci-$(CONFIG_MACH_IXP4XX_OF)	+= ixp4xx-of.o



obj-pci-$(CONFIG_ARCH_IXDP4XX)		+= ixdp425-pci.o

obj-pci-$(CONFIG_MACH_IXDPG425)		+= ixdpg425-pci.o

obj-pci-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-pci.o

obj-pci-$(CONFIG_MACH_GTWX5715)		+= gtwx5715-pci.o
@@ -18,7 +17,6 @@ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o 


obj-y	+= common.o



obj-$(CONFIG_ARCH_IXDP4XX)	+= ixdp425-setup.o

obj-$(CONFIG_MACH_IXDPG425)	+= coyote-setup.o

obj-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-setup.o

obj-$(CONFIG_MACH_GTWX5715)	+= gtwx5715-setup.o

arch/arm/mach-ixp4xx/ixdp425-pci.c

deleted100644 → 0
+0 −75
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * arch/arm/mach-ixp4xx/ixdp425-pci.c

 *

 * IXDP425 board-level PCI initialization

 *

 * Copyright (C) 2002 Intel Corporation.

 * Copyright (C) 2003-2004 MontaVista Software, Inc.

 *

 * Maintainer: Deepak Saxena <dsaxena@plexity.net>

 */



#include <linux/kernel.h>

#include <linux/pci.h>

#include <linux/init.h>

#include <linux/irq.h>

#include <linux/delay.h>

#include <asm/mach/pci.h>

#include <asm/irq.h>

#include <mach/hardware.h>

#include <asm/mach-types.h>



#include "irqs.h"



#define MAX_DEV		4

#define IRQ_LINES	4



/* PCI controller GPIO to IRQ pin mappings */

#define INTA		11

#define INTB		10

#define INTC		9

#define INTD		8





void __init ixdp425_pci_preinit(void)

{

	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);

	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);

	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);

	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);

	ixp4xx_pci_preinit();

}



static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

{

	static int pci_irq_table[IRQ_LINES] = {

		IXP4XX_GPIO_IRQ(INTA),

		IXP4XX_GPIO_IRQ(INTB),

		IXP4XX_GPIO_IRQ(INTC),

		IXP4XX_GPIO_IRQ(INTD)

	};



	if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)

		return pci_irq_table[(slot + pin - 2) % 4];



	return -1;

}



struct hw_pci ixdp425_pci __initdata = {

	.nr_controllers = 1,

	.ops		= &ixp4xx_ops,

	.preinit	= ixdp425_pci_preinit,

	.setup		= ixp4xx_setup,

	.map_irq	= ixdp425_map_irq,

};



int __init ixdp425_pci_init(void)

{

	if (machine_is_ixdp425() || machine_is_ixcdp1100() ||

			machine_is_ixdp465() || machine_is_kixrp435())

		pci_common_init(&ixdp425_pci);

	return 0;

}



subsys_initcall(ixdp425_pci_init);

arch/arm/mach-ixp4xx/ixdp425-setup.c

deleted100644 → 0
+0 −339
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * arch/arm/mach-ixp4xx/ixdp425-setup.c

 *

 * IXDP425/IXCDP1100 board-setup

 *

 * Copyright (C) 2003-2005 MontaVista Software, Inc.

 *

 * Author: Deepak Saxena <dsaxena@plexity.net>

 */



#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/device.h>

#include <linux/serial.h>

#include <linux/tty.h>

#include <linux/serial_8250.h>

#include <linux/gpio/machine.h>

#include <linux/io.h>

#include <linux/mtd/mtd.h>

#include <linux/mtd/rawnand.h>

#include <linux/mtd/partitions.h>

#include <linux/mtd/platnand.h>

#include <linux/delay.h>

#include <linux/gpio.h>

#include <asm/types.h>

#include <asm/setup.h>

#include <asm/memory.h>

#include <mach/hardware.h>

#include <asm/mach-types.h>

#include <asm/irq.h>

#include <asm/mach/arch.h>

#include <asm/mach/flash.h>



#include "irqs.h"



#define IXDP425_SDA_PIN		7

#define IXDP425_SCL_PIN		6



/* NAND Flash pins */

#define IXDP425_NAND_NCE_PIN	12



#define IXDP425_NAND_CMD_BYTE	0x01

#define IXDP425_NAND_ADDR_BYTE	0x02



static struct flash_platform_data ixdp425_flash_data = {

	.map_name	= "cfi_probe",

	.width		= 2,

};



static struct resource ixdp425_flash_resource = {

	.flags		= IORESOURCE_MEM,

};



static struct platform_device ixdp425_flash = {

	.name		= "IXP4XX-Flash",

	.id		= 0,

	.dev		= {

		.platform_data = &ixdp425_flash_data,

	},

	.num_resources	= 1,

	.resource	= &ixdp425_flash_resource,

};



#if defined(CONFIG_MTD_NAND_PLATFORM) || \

    defined(CONFIG_MTD_NAND_PLATFORM_MODULE)



static struct mtd_partition ixdp425_partitions[] = {

	{

		.name	= "ixp400 NAND FS 0",

		.offset	= 0,

		.size 	= SZ_8M

	}, {

		.name	= "ixp400 NAND FS 1",

		.offset	= MTDPART_OFS_APPEND,

		.size	= MTDPART_SIZ_FULL

	},

};



static void

ixdp425_flash_nand_cmd_ctrl(struct nand_chip *this, int cmd, unsigned int ctrl)

{

	int offset = (int)nand_get_controller_data(this);



	if (ctrl & NAND_CTRL_CHANGE) {

		if (ctrl & NAND_NCE) {

			gpio_set_value(IXDP425_NAND_NCE_PIN, 0);

			udelay(5);

		} else

			gpio_set_value(IXDP425_NAND_NCE_PIN, 1);



		offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;

		offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;

		nand_set_controller_data(this, (void *)offset);

	}



	if (cmd != NAND_CMD_NONE)

		writeb(cmd, this->legacy.IO_ADDR_W + offset);

}



static struct platform_nand_data ixdp425_flash_nand_data = {

	.chip = {

		.nr_chips		= 1,

		.chip_delay		= 30,

		.partitions	 	= ixdp425_partitions,

		.nr_partitions	 	= ARRAY_SIZE(ixdp425_partitions),

	},

	.ctrl = {

		.cmd_ctrl 		= ixdp425_flash_nand_cmd_ctrl

	}

};



static struct resource ixdp425_flash_nand_resource = {

	.flags		= IORESOURCE_MEM,

};



static struct platform_device ixdp425_flash_nand = {

	.name		= "gen_nand",

	.id		= -1,

	.dev		= {

		.platform_data = &ixdp425_flash_nand_data,

	},

	.num_resources	= 1,

	.resource	= &ixdp425_flash_nand_resource,

};

#endif	/* CONFIG_MTD_NAND_PLATFORM */



static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = {

	.dev_id		= "i2c-gpio.0",

	.table		= {

		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN,

				NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),

		GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN,

				NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),

	},

};



static struct platform_device ixdp425_i2c_gpio = {

	.name		= "i2c-gpio",

	.id		= 0,

	.dev	 = {

		.platform_data	= NULL,

	},

};



static struct resource ixdp425_uart_resources[] = {

	{

		.start		= IXP4XX_UART1_BASE_PHYS,

		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,

		.flags		= IORESOURCE_MEM

	},

	{

		.start		= IXP4XX_UART2_BASE_PHYS,

		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,

		.flags		= IORESOURCE_MEM

	}

};



static struct plat_serial8250_port ixdp425_uart_data[] = {

	{

		.mapbase	= IXP4XX_UART1_BASE_PHYS,

		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,

		.irq		= IRQ_IXP4XX_UART1,

		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,

		.iotype		= UPIO_MEM,

		.regshift	= 2,

		.uartclk	= IXP4XX_UART_XTAL,

	},

	{

		.mapbase	= IXP4XX_UART2_BASE_PHYS,

		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,

		.irq		= IRQ_IXP4XX_UART2,

		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,

		.iotype		= UPIO_MEM,

		.regshift	= 2,

		.uartclk	= IXP4XX_UART_XTAL,

	},

	{ },

};



static struct platform_device ixdp425_uart = {

	.name			= "serial8250",

	.id			= PLAT8250_DEV_PLATFORM,

	.dev.platform_data	= ixdp425_uart_data,

	.num_resources		= 2,

	.resource		= ixdp425_uart_resources

};



/* Built-in 10/100 Ethernet MAC interfaces */

static struct resource ixp425_npeb_resources[] = {

	{

		.start		= IXP4XX_EthB_BASE_PHYS,

		.end		= IXP4XX_EthB_BASE_PHYS + 0x0fff,

		.flags		= IORESOURCE_MEM,

	},

};



static struct resource ixp425_npec_resources[] = {

	{

		.start		= IXP4XX_EthC_BASE_PHYS,

		.end		= IXP4XX_EthC_BASE_PHYS + 0x0fff,

		.flags		= IORESOURCE_MEM,

	},

};



static struct eth_plat_info ixdp425_plat_eth[] = {

	{

		.phy		= 0,

		.rxq		= 3,

		.txreadyq	= 20,

	}, {

		.phy		= 1,

		.rxq		= 4,

		.txreadyq	= 21,

	}

};



static struct platform_device ixdp425_eth[] = {

	{

		.name			= "ixp4xx_eth",

		.id			= IXP4XX_ETH_NPEB,

		.dev.platform_data	= ixdp425_plat_eth,

		.num_resources		= ARRAY_SIZE(ixp425_npeb_resources),

		.resource		= ixp425_npeb_resources,

	}, {

		.name			= "ixp4xx_eth",

		.id			= IXP4XX_ETH_NPEC,

		.dev.platform_data	= ixdp425_plat_eth + 1,

		.num_resources		= ARRAY_SIZE(ixp425_npec_resources),

		.resource		= ixp425_npec_resources,

	}

};



static struct platform_device *ixdp425_devices[] __initdata = {

	&ixdp425_i2c_gpio,

	&ixdp425_flash,

#if defined(CONFIG_MTD_NAND_PLATFORM) || \

    defined(CONFIG_MTD_NAND_PLATFORM_MODULE)

	&ixdp425_flash_nand,

#endif

	&ixdp425_uart,

	&ixdp425_eth[0],

	&ixdp425_eth[1],

};



static void __init ixdp425_init(void)

{

	ixp4xx_sys_init();



	ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);

	ixdp425_flash_resource.end =

		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;



#if defined(CONFIG_MTD_NAND_PLATFORM) || \

    defined(CONFIG_MTD_NAND_PLATFORM_MODULE)

	ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),

	ixdp425_flash_nand_resource.end   = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;



	gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin");

	gpio_direction_output(IXDP425_NAND_NCE_PIN, 0);



	/* Configure expansion bus for NAND Flash */

	*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |

			  IXP4XX_EXP_BUS_STROBE_T(1) |	/* extend by 1 clock */

			  IXP4XX_EXP_BUS_CYCLES(0) |	/* Intel cycles */

			  IXP4XX_EXP_BUS_SIZE(0) |	/* 512bytes addr space*/

			  IXP4XX_EXP_BUS_WR_EN |

			  IXP4XX_EXP_BUS_BYTE_EN;	/* 8 bit data bus */

#endif



	if (cpu_is_ixp43x()) {

		ixdp425_uart.num_resources = 1;

		ixdp425_uart_data[1].flags = 0;

	}



	gpiod_add_lookup_table(&ixdp425_i2c_gpiod_table);

	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));

}



#ifdef CONFIG_ARCH_IXDP425

MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")

	/* Maintainer: MontaVista Software, Inc. */

	.map_io		= ixp4xx_map_io,

	.init_early	= ixp4xx_init_early,

	.init_irq	= ixp4xx_init_irq,

	.init_time	= ixp4xx_timer_init,

	.atag_offset	= 0x100,

	.init_machine	= ixdp425_init,

#if defined(CONFIG_PCI)

	.dma_zone_size	= SZ_64M,

#endif

	.restart	= ixp4xx_restart,

MACHINE_END

#endif



#ifdef CONFIG_MACH_IXDP465

MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")

	/* Maintainer: MontaVista Software, Inc. */

	.map_io		= ixp4xx_map_io,

	.init_early	= ixp4xx_init_early,

	.init_irq	= ixp4xx_init_irq,

	.init_time	= ixp4xx_timer_init,

	.atag_offset	= 0x100,

	.init_machine	= ixdp425_init,

#if defined(CONFIG_PCI)

	.dma_zone_size	= SZ_64M,

#endif

MACHINE_END

#endif



#ifdef CONFIG_ARCH_PRPMC1100

MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")

	/* Maintainer: MontaVista Software, Inc. */

	.map_io		= ixp4xx_map_io,

	.init_early	= ixp4xx_init_early,

	.init_irq	= ixp4xx_init_irq,

	.init_time	= ixp4xx_timer_init,

	.atag_offset	= 0x100,

	.init_machine	= ixdp425_init,

#if defined(CONFIG_PCI)

	.dma_zone_size	= SZ_64M,

#endif

MACHINE_END

#endif



#ifdef CONFIG_MACH_KIXRP435

MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")

	/* Maintainer: MontaVista Software, Inc. */

	.map_io		= ixp4xx_map_io,

	.init_early	= ixp4xx_init_early,

	.init_irq	= ixp4xx_init_irq,

	.init_time	= ixp4xx_timer_init,

	.atag_offset	= 0x100,

	.init_machine	= ixdp425_init,

#if defined(CONFIG_PCI)

	.dma_zone_size	= SZ_64M,

#endif

MACHINE_END

#endif