Commit 73a901d0 authored by Maciej Purski's avatar Maciej Purski Committed by Krzysztof Kozlowski
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ARM: dts: exynos: Add soc node to exynos4 



Soc nodes are used in other exynos DTS. Exynos4 boards should use them
as well.

Signed-off-by: default avatarMaciej Purski <m.purski@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent ca42d8d8

arch/arm/boot/dts/exynos4.dtsi

+872 −855
Original line number Diff line number Diff line
@@ -52,13 +52,21 @@ 
		serial3 = &serial_3;

	};



	soc: soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		clock_audss: clock-controller@3810000 {

			compatible = "samsung,exynos4210-audss-clock";

			reg = <0x03810000 0x0C>;

			#clock-cells = <1>;

			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,

			 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;

		clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";

				 <&clock CLK_SCLK_AUDIO0>,

				 <&clock CLK_SCLK_AUDIO0>;

			clock-names = "pll_ref", "pll_in", "sclk_audio",

				      "sclk_pcm_in";

		};



		i2s0: i2s@3830000 {
@@ -208,7 +216,8 @@ 
				compatible = "samsung,exynos4210-fimc";

				reg = <0x11800000 0x1000>;

				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;

				clocks = <&clock CLK_FIMC0>,

					 <&clock CLK_SCLK_FIMC0>;

				clock-names = "fimc", "sclk_fimc";

				power-domains = <&pd_cam>;

				samsung,sysreg = <&sys_reg>;
@@ -220,7 +229,8 @@ 
				compatible = "samsung,exynos4210-fimc";

				reg = <0x11810000 0x1000>;

				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;

				clocks = <&clock CLK_FIMC1>,

					 <&clock CLK_SCLK_FIMC1>;

				clock-names = "fimc", "sclk_fimc";

				power-domains = <&pd_cam>;

				samsung,sysreg = <&sys_reg>;
@@ -232,7 +242,8 @@ 
				compatible = "samsung,exynos4210-fimc";

				reg = <0x11820000 0x1000>;

				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;

				clocks = <&clock CLK_FIMC2>,

					 <&clock CLK_SCLK_FIMC2>;

				clock-names = "fimc", "sclk_fimc";

				power-domains = <&pd_cam>;

				samsung,sysreg = <&sys_reg>;
@@ -244,7 +255,8 @@ 
				compatible = "samsung,exynos4210-fimc";

				reg = <0x11830000 0x1000>;

				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;

				clocks = <&clock CLK_FIMC3>,

					 <&clock CLK_SCLK_FIMC3>;

				clock-names = "fimc", "sclk_fimc";

				power-domains = <&pd_cam>;

				samsung,sysreg = <&sys_reg>;
@@ -256,7 +268,8 @@ 
				compatible = "samsung,exynos4210-csis";

				reg = <0x11880000 0x4000>;

				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;

				clocks = <&clock CLK_CSIS0>,

					 <&clock CLK_SCLK_CSIS0>;

				clock-names = "csis", "sclk_csis";

				bus-width = <4>;

				power-domains = <&pd_cam>;
@@ -271,7 +284,8 @@ 
				compatible = "samsung,exynos4210-csis";

				reg = <0x11890000 0x4000>;

				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;

				clocks = <&clock CLK_CSIS1>,

					 <&clock CLK_SCLK_CSIS1>;

				clock-names = "csis", "sclk_csis";

				bus-width = <2>;

				power-domains = <&pd_cam>;
@@ -748,10 +762,11 @@ 
			compatible = "samsung,exynos4210-hdmi";

			reg = <0x12D00000 0x70000>;

			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",

			"mout_hdmi";

			clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",

				      "sclk_hdmiphy", "mout_hdmi";

			clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,

			<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,

				 <&clock CLK_SCLK_PIXEL>,

				 <&clock CLK_SCLK_HDMIPHY>,

				 <&clock CLK_MOUT_HDMI>;

			phy = <&hdmi_i2c_phy>;

			power-domains = <&pd_tv>;
@@ -984,7 +999,8 @@ 
			interrupt-parent = <&combiner>;

			interrupts = <5 0>;

			clock-names = "sysmmu", "master";

		clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;

			clocks = <&clock CLK_SMMU_ROTATOR>,

				 <&clock CLK_ROTATOR>;

			#iommu-cells = <0>;

		};
@@ -1014,3 +1030,4 @@ 
			clock-names = "secss";

		};

	};

};