Commit 7391f82f authored by Herbert Xu's avatar Herbert Xu Committed by JangShui Yang
Browse files

crypto: hisilicon/sec2 - Remove cfb and ofb 

mainline inclusion
from mainline-v6.8-rc1
commit 1c90a1b43bc34eaf9c8913238f408a1317eab43f
category: cleanup
bugzilla: https://gitee.com/openeuler/kernel/issues/I925L9
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1c90a1b43bc34eaf9c8913238f408a1317eab43f



----------------------------------------------------------------------

Remove the unused CFB/OFB implementation.

Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: default avatarJangShui Yang <yangjiangshui@h-partners.com>
parent bbd797fa

drivers/crypto/hisilicon/sec2/sec_crypto.c

+0 −26
Original line number Diff line number Diff line
@@ -879,15 +879,11 @@ static int sec_setkey_##name(struct crypto_skcipher *tfm, const u8 *key,\ 
GEN_SEC_SETKEY_FUNC(aes_ecb, SEC_CALG_AES, SEC_CMODE_ECB)

GEN_SEC_SETKEY_FUNC(aes_cbc, SEC_CALG_AES, SEC_CMODE_CBC)

GEN_SEC_SETKEY_FUNC(aes_xts, SEC_CALG_AES, SEC_CMODE_XTS)

GEN_SEC_SETKEY_FUNC(aes_ofb, SEC_CALG_AES, SEC_CMODE_OFB)

GEN_SEC_SETKEY_FUNC(aes_cfb, SEC_CALG_AES, SEC_CMODE_CFB)

GEN_SEC_SETKEY_FUNC(aes_ctr, SEC_CALG_AES, SEC_CMODE_CTR)

GEN_SEC_SETKEY_FUNC(3des_ecb, SEC_CALG_3DES, SEC_CMODE_ECB)

GEN_SEC_SETKEY_FUNC(3des_cbc, SEC_CALG_3DES, SEC_CMODE_CBC)

GEN_SEC_SETKEY_FUNC(sm4_xts, SEC_CALG_SM4, SEC_CMODE_XTS)

GEN_SEC_SETKEY_FUNC(sm4_cbc, SEC_CALG_SM4, SEC_CMODE_CBC)

GEN_SEC_SETKEY_FUNC(sm4_ofb, SEC_CALG_SM4, SEC_CMODE_OFB)

GEN_SEC_SETKEY_FUNC(sm4_cfb, SEC_CALG_SM4, SEC_CMODE_CFB)

GEN_SEC_SETKEY_FUNC(sm4_ctr, SEC_CALG_SM4, SEC_CMODE_CTR)



static int sec_cipher_pbuf_map(struct sec_ctx *ctx, struct sec_req *req,
@@ -2032,8 +2028,6 @@ static int sec_skcipher_cryptlen_check(struct sec_ctx *ctx, 
			ret = -EINVAL;

		}

		break;

	case SEC_CMODE_CFB:

	case SEC_CMODE_OFB:

	case SEC_CMODE_CTR:

		if (unlikely(ctx->sec->qm.ver < QM_HW_V3)) {

			dev_err(dev, "skcipher HW version error!\n");
@@ -2197,16 +2191,6 @@ static struct sec_skcipher sec_skciphers[] = { 
		.alg = SEC_SKCIPHER_ALG("xts(aes)", sec_setkey_aes_xts,	SEC_XTS_MIN_KEY_SIZE,

					SEC_XTS_MAX_KEY_SIZE, AES_BLOCK_SIZE, AES_BLOCK_SIZE),

	},

	{

		.alg_msk = BIT(4),

		.alg = SEC_SKCIPHER_ALG("ofb(aes)", sec_setkey_aes_ofb,	AES_MIN_KEY_SIZE,

					AES_MAX_KEY_SIZE, SEC_MIN_BLOCK_SZ, AES_BLOCK_SIZE),

	},

	{

		.alg_msk = BIT(5),

		.alg = SEC_SKCIPHER_ALG("cfb(aes)", sec_setkey_aes_cfb,	AES_MIN_KEY_SIZE,

					AES_MAX_KEY_SIZE, SEC_MIN_BLOCK_SZ, AES_BLOCK_SIZE),

	},

	{

		.alg_msk = BIT(12),

		.alg = SEC_SKCIPHER_ALG("cbc(sm4)", sec_setkey_sm4_cbc,	AES_MIN_KEY_SIZE,
@@ -2222,16 +2206,6 @@ static struct sec_skcipher sec_skciphers[] = { 
		.alg = SEC_SKCIPHER_ALG("xts(sm4)", sec_setkey_sm4_xts,	SEC_XTS_MIN_KEY_SIZE,

					SEC_XTS_MIN_KEY_SIZE, AES_BLOCK_SIZE, AES_BLOCK_SIZE),

	},

	{

		.alg_msk = BIT(15),

		.alg = SEC_SKCIPHER_ALG("ofb(sm4)", sec_setkey_sm4_ofb,	AES_MIN_KEY_SIZE,

					AES_MIN_KEY_SIZE, SEC_MIN_BLOCK_SZ, AES_BLOCK_SIZE),

	},

	{

		.alg_msk = BIT(16),

		.alg = SEC_SKCIPHER_ALG("cfb(sm4)", sec_setkey_sm4_cfb,	AES_MIN_KEY_SIZE,

					AES_MIN_KEY_SIZE, SEC_MIN_BLOCK_SZ, AES_BLOCK_SIZE),

	},

	{

		.alg_msk = BIT(23),

		.alg = SEC_SKCIPHER_ALG("ecb(des3_ede)", sec_setkey_3des_ecb, SEC_DES3_3KEY_SIZE,

drivers/crypto/hisilicon/sec2/sec_crypto.h

+0 −2
Original line number Diff line number Diff line
@@ -37,8 +37,6 @@ enum sec_mac_len { 
enum sec_cmode {

	SEC_CMODE_ECB    = 0x0,

	SEC_CMODE_CBC    = 0x1,

	SEC_CMODE_CFB    = 0x2,

	SEC_CMODE_OFB    = 0x3,

	SEC_CMODE_CTR    = 0x4,

	SEC_CMODE_CCM    = 0x5,

	SEC_CMODE_GCM    = 0x6,

drivers/crypto/hisilicon/sec2/sec_main.c

+1 −1
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ static const struct hisi_qm_cap_info sec_basic_info[] = { 
	{SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4},

	{SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4},

	{SEC_CORE_ENABLE_BITMAP, 0x3140, 32, GENMASK(31, 0), 0x17F, 0x17F, 0xF},

	{SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x187F0FF},

	{SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x18670CF},

	{SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C},

	{SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},

	{SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},