perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids

mainline inclusion
from mainline-v5.14-rc1
commit d18216fa
category: feature
feature: SPR PMU core event enhancement
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I596BF



Intel-SIG: commit d18216fa ("perf/x86/intel: Add more events requires
FRONTEND MSR on Sapphire Rapids")

-------------------------------------

perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids

On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which
rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the
count value is not correct.

Update intel_spr_extra_regs[] to support them.

Fixes: 61b985e3 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1624029174-122219-3-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Jason Zeng <jason.zeng@intel.com>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>