Commit 733f7e9c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'v6.4-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 

Pull crypto updates from Herbert Xu:
 "API:
   - Total usage stats now include all that returned errors (instead of
     just some)
   - Remove maximum hash statesize limit
   - Add cloning support for hmac and unkeyed hashes
   - Demote BUG_ON in crypto_unregister_alg to a WARN_ON

  Algorithms:
   - Use RIP-relative addressing on x86 to prepare for PIE build
   - Add accelerated AES/GCM stitched implementation on powerpc P10
   - Add some test vectors for cmac(camellia)
   - Remove failure case where jent is unavailable outside of FIPS mode
     in drbg
   - Add permanent and intermittent health error checks in jitter RNG

  Drivers:
   - Add support for 402xx devices in qat
   - Add support for HiSTB TRNG
   - Fix hash concurrency issues in stm32
   - Add OP-TEE firmware support in caam"

* tag 'v6.4-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (139 commits)
  i2c: designware: Add doorbell support for Mendocino
  i2c: designware: Use PCI PSP driver for communication
  powerpc: Move Power10 feature PPC_MODULE_FEATURE_P10
  crypto: p10-aes-gcm - Remove POWER10_CPU dependency
  crypto: testmgr - Add some test vectors for cmac(camellia)
  crypto: cryptd - Add support for cloning hashes
  crypto: cryptd - Convert hash to use modern init_tfm/exit_tfm
  crypto: hmac - Add support for cloning
  crypto: hash - Add crypto_clone_ahash/shash
  crypto: api - Add crypto_clone_tfm
  crypto: api - Add crypto_tfm_get
  crypto: x86/sha - Use local .L symbols for code
  crypto: x86/crc32 - Use local .L symbols for code
  crypto: x86/aesni - Use local .L symbols for code
  crypto: x86/sha256 - Use RIP-relative addressing
  crypto: x86/ghash - Use RIP-relative addressing
  crypto: x86/des3 - Use RIP-relative addressing
  crypto: x86/crc32c - Use RIP-relative addressing
  crypto: x86/cast6 - Use RIP-relative addressing
  crypto: x86/cast5 - Use RIP-relative addressing
  ...
parents 98f99e67 482c84e9

Documentation/devicetree/bindings/crypto/qcom-qce.txt

deleted100644 → 0
+0 −25
Original line number Diff line number Diff line 
Qualcomm crypto engine driver



Required properties:



- compatible  : should be "qcom,crypto-v5.1"

- reg         : specifies base physical address and size of the registers map

- clocks      : phandle to clock-controller plus clock-specifier pair

- clock-names : "iface" clocks register interface

                "bus" clocks data transfer interface

                "core" clocks rest of the crypto block

- dmas        : DMA specifiers for tx and rx dma channels. For more see

                Documentation/devicetree/bindings/dma/dma.txt

- dma-names   : DMA request names should be "rx" and "tx"



Example:

	crypto@fd45a000 {

		compatible = "qcom,crypto-v5.1";

		reg = <0xfd45a000 0x6000>;

		clocks = <&gcc GCC_CE2_AHB_CLK>,

			 <&gcc GCC_CE2_AXI_CLK>,

			 <&gcc GCC_CE2_CLK>;

		clock-names = "iface", "bus", "core";

		dmas = <&cryptobam 2>, <&cryptobam 3>;

		dma-names = "rx", "tx";

	};

Documentation/devicetree/bindings/crypto/qcom-qce.yaml

0 → 100644
+123 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm crypto engine driver



maintainers:

  - Bhupesh Sharma <bhupesh.sharma@linaro.org>



description:

  This document defines the binding for the QCE crypto

  controller found on Qualcomm parts.



properties:

  compatible:

    oneOf:

      - const: qcom,crypto-v5.1

        deprecated: true

        description: Kept only for ABI backward compatibility



      - const: qcom,crypto-v5.4

        deprecated: true

        description: Kept only for ABI backward compatibility



      - items:

          - enum:

              - qcom,ipq6018-qce

              - qcom,ipq8074-qce

              - qcom,msm8996-qce

              - qcom,sdm845-qce

          - const: qcom,ipq4019-qce

          - const: qcom,qce



      - items:

          - enum:

              - qcom,sm8250-qce

              - qcom,sm8350-qce

              - qcom,sm8450-qce

              - qcom,sm8550-qce

          - const: qcom,sm8150-qce

          - const: qcom,qce



  reg:

    maxItems: 1



  clocks:

    items:

      - description: iface clocks register interface.

      - description: bus clocks data transfer interface.

      - description: core clocks rest of the crypto block.



  clock-names:

    items:

      - const: iface

      - const: bus

      - const: core



  iommus:

    minItems: 1

    maxItems: 8

    description:

      phandle to apps_smmu node with sid mask.



  interconnects:

    maxItems: 1

    description:

      Interconnect path between qce crypto and main memory.



  interconnect-names:

    const: memory



  dmas:

    items:

      - description: DMA specifiers for rx dma channel.

      - description: DMA specifiers for tx dma channel.



  dma-names:

    items:

      - const: rx

      - const: tx



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,crypto-v5.1

              - qcom,crypto-v5.4

              - qcom,ipq4019-qce



    then:

      required:

        - clocks

        - clock-names



required:

  - compatible

  - reg

  - dmas

  - dma-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-apq8084.h>

    crypto-engine@fd45a000 {

        compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";

        reg = <0xfd45a000 0x6000>;

        clocks = <&gcc GCC_CE2_AHB_CLK>,

                 <&gcc GCC_CE2_AXI_CLK>,

                 <&gcc GCC_CE2_CLK>;

        clock-names = "iface", "bus", "core";

        dmas = <&cryptobam 2>, <&cryptobam 3>;

        dma-names = "rx", "tx";

        iommus = <&apps_smmu 0x584 0x0011>,

                 <&apps_smmu 0x586 0x0011>,

                 <&apps_smmu 0x594 0x0011>,

                 <&apps_smmu 0x596 0x0011>;

    };

MAINTAINERS

+17 −16
Original line number Diff line number Diff line
@@ -2269,7 +2269,7 @@ F: arch/arm/boot/dts/intel-ixp* 
F:	arch/arm/mach-ixp4xx/

F:	drivers/bus/intel-ixp4xx-eb.c

F:	drivers/clocksource/timer-ixp4xx.c

F:	drivers/crypto/ixp4xx_crypto.c

F:	drivers/crypto/intel/ixp4xx/ixp4xx_crypto.c

F:	drivers/gpio/gpio-ixp4xx.c

F:	drivers/irqchip/irq-ixp4xx.c








@@ -10391,7 +10391,7 @@ INTEL IXP4XX CRYPTO SUPPORT







M:	Corentin Labbe <clabbe@baylibre.com>









L:	linux-crypto@vger.kernel.org









S:	Maintained









F:	drivers/crypto/ixp4xx_crypto.c









F:	drivers/crypto/intel/ixp4xx/ixp4xx_crypto.c

















INTEL ISHTP ECLITE DRIVER









M:	Sumesh K Naduvalath <sumesh.k.naduvalath@intel.com>








@@ -10426,11 +10426,11 @@ INTEL KEEM BAY OCS AES/SM4 CRYPTO DRIVER







M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>









S:	Maintained









F:	Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml









F:	drivers/crypto/keembay/Kconfig









F:	drivers/crypto/keembay/Makefile









F:	drivers/crypto/keembay/keembay-ocs-aes-core.c









F:	drivers/crypto/keembay/ocs-aes.c









F:	drivers/crypto/keembay/ocs-aes.h









F:	drivers/crypto/intel/keembay/Kconfig









F:	drivers/crypto/intel/keembay/Makefile









F:	drivers/crypto/intel/keembay/keembay-ocs-aes-core.c









F:	drivers/crypto/intel/keembay/ocs-aes.c









F:	drivers/crypto/intel/keembay/ocs-aes.h

















INTEL KEEM BAY OCS ECC CRYPTO DRIVER









M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>








@@ -10438,20 +10438,20 @@ M:	Prabhjot Khurana <prabhjot.khurana@intel.com>







M:	Mark Gross <mgross@linux.intel.com>









S:	Maintained









F:	Documentation/devicetree/bindings/crypto/intel,keembay-ocs-ecc.yaml









F:	drivers/crypto/keembay/Kconfig









F:	drivers/crypto/keembay/Makefile









F:	drivers/crypto/keembay/keembay-ocs-ecc.c









F:	drivers/crypto/intel/keembay/Kconfig









F:	drivers/crypto/intel/keembay/Makefile









F:	drivers/crypto/intel/keembay/keembay-ocs-ecc.c

















INTEL KEEM BAY OCS HCU CRYPTO DRIVER









M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>









M:	Declan Murphy <declan.murphy@intel.com>









S:	Maintained









F:	Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml









F:	drivers/crypto/keembay/Kconfig









F:	drivers/crypto/keembay/Makefile









F:	drivers/crypto/keembay/keembay-ocs-hcu-core.c









F:	drivers/crypto/keembay/ocs-hcu.c









F:	drivers/crypto/keembay/ocs-hcu.h









F:	drivers/crypto/intel/keembay/Kconfig









F:	drivers/crypto/intel/keembay/Makefile









F:	drivers/crypto/intel/keembay/keembay-ocs-hcu-core.c









F:	drivers/crypto/intel/keembay/ocs-hcu.c









F:	drivers/crypto/intel/keembay/ocs-hcu.h

















INTEL THUNDER BAY EMMC PHY DRIVER









M:	Nandhini Srikandan <nandhini.srikandan@intel.com>








@@ -17027,7 +17027,7 @@ QAT DRIVER







M:	Giovanni Cabiddu <giovanni.cabiddu@intel.com>









L:	qat-linux@intel.com









S:	Supported









F:	drivers/crypto/qat/









F:	drivers/crypto/intel/qat/

















QCOM AUDIO (ASoC) DRIVERS









M:	Srinivas Kandagatla <srinivas.kandagatla@linaro.org>








@@ -17295,6 +17295,7 @@ M:	Thara Gopinath <thara.gopinath@gmail.com>







L:	linux-crypto@vger.kernel.org









L:	linux-arm-msm@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/crypto/qcom-qce.yaml









F:	drivers/crypto/qce/

















QUALCOMM EMAC GIGABIT ETHERNET DRIVER

























arch/arm64/boot/dts/qcom/sm8550.dtsi



+1
−1






























Original line number
Diff line number
Diff line







@@ -1850,7 +1850,7 @@







		};



















		crypto: crypto@1de0000 {









			compatible = "qcom,sm8550-qce";









			compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";









			reg = <0x0 0x01dfa000 0x0 0x6000>;









			dmas = <&cryptobam 4>, <&cryptobam 5>;









			dma-names = "rx", "tx";
































arch/arm64/crypto/aes-neonbs-core.S



+5
−4






























Original line number
Diff line number
Diff line







@@ -15,6 +15,7 @@







 */



















#include <linux/linkage.h>









#include <linux/cfi_types.h>









#include <asm/assembler.h>



















	.text








@@ -620,12 +621,12 @@ SYM_FUNC_END(aesbs_decrypt8)







	.endm



















	.align		4









SYM_FUNC_START(aesbs_ecb_encrypt)









SYM_TYPED_FUNC_START(aesbs_ecb_encrypt)









	__ecb_crypt	aesbs_encrypt8, v0, v1, v4, v6, v3, v7, v2, v5









SYM_FUNC_END(aesbs_ecb_encrypt)



















	.align		4









SYM_FUNC_START(aesbs_ecb_decrypt)









SYM_TYPED_FUNC_START(aesbs_ecb_decrypt)









	__ecb_crypt	aesbs_decrypt8, v0, v1, v6, v4, v2, v7, v3, v5









SYM_FUNC_END(aesbs_ecb_decrypt)


















@@ -799,11 +800,11 @@ SYM_FUNC_END(__xts_crypt8)







	ret









	.endm



















SYM_FUNC_START(aesbs_xts_encrypt)









SYM_TYPED_FUNC_START(aesbs_xts_encrypt)









	__xts_crypt	aesbs_encrypt8, v0, v1, v4, v6, v3, v7, v2, v5









SYM_FUNC_END(aesbs_xts_encrypt)



















SYM_FUNC_START(aesbs_xts_decrypt)









SYM_TYPED_FUNC_START(aesbs_xts_decrypt)









	__xts_crypt	aesbs_decrypt8, v0, v1, v6, v4, v2, v7, v3, v5









SYM_FUNC_END(aesbs_xts_decrypt)